2000 Fairchild Semiconductor Corporation
DS006525
www.fairchildsemi.com
September 1986
Revised February 2000
DM7473 Dual
Mast
er-
S
l
ave J-K Fl
ip-
F
lops wit
h
Cl
ear and Com
p
l
e
mentar
y
Out
puts
DM7473
Dual Master-Slave J-K Flip-Flops
with Clear and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops after a complete clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave. The logic states of the J and K
inputs must not be allowed to change while the clock is
HIGH. Data transfers to the outputs on the falling edge of
the clock pulse. A LOW logic level on the clear input will
reset the outputs regardless of the logic states of the other
inputs.
Ordering Code:
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
=
Positive pulse data. the J and K inputs must be held constant while
the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse.
Q
0
=
The output logic level before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each HIGH level clock pulse.
Order Number
Package Number
Package Description
DM7473N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
CLR
CLK
J
K
Q
Q
L
X
X
X
L
H
H
L
L
Q
0
Q
0
H
H
L
H
L
H
L
H
L
H
H
H
H
Toggle
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2
D
M
7473
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: The symbol (
,
) indicates the edge of the clock pulse is used for reference: (
) for rising edge, (
) for falling edge.
Note 3: T
A
=
25
C and V
CC
=
5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 4: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 5: Not more than one output should be shorted at a time.
Note 6: With all outputs OPEN, I
CC
is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock input grounded.
Switching Characteristics
at V
CC
=
5V and T
A
=
25
C
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
0.4
mA
I
OL
LOW Level Output Current
16
mA
f
CLK
Clock Frequency (Note 3)
0
15
MHz
t
W
Pulse Width
Clock HIGH
20
(Note 3)
Clock LOW
47
ns
Clear LOW
25
t
SU
Input Setup Time (Note 2)(Note 3)
0
ns
t
H
Input Hold Time (Note 2)(Note 3)
0
ns
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ (Note 4)
Max
Units
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
12 mA
-
1.5
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.4
3.4
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW
Level V
CC
=
Min, I
OL
=
Max
0.2
0.4
V
Output Voltage
V
IH
=
Min, V
IL
=
Max
I
I
Input Current @ Max Input Voltage V
CC
=
Max, V
I
=
5.5V
1
mA
I
IH
HIGH Level
V
CC
=
Max
J, K
40
Input Current
V
I
=
2.4V
Clock
80
A
Clear
80
I
IL
LOW Level Input
V
CC
=
Max
J, K
-
1.6
Current
V
I
=
0.4V
Clock
-
3.2
mA
Clear
-
3.2
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 5)
-
18
-
55
mA
I
CC
Supply Current
V
CC
=
Max, (Note 6)
18
34
mA
Symbol
Parameter
From (Input)
R
L
=
400
, C
L
=
15 pF
Units
To (Output)
Min
Max
f
MAX
Maximum Clock Frequency
15
MHz
t
PHL
Propagation Delay Time HIGH-to-LOW Level Output
Clear to Q
40
ns
t
PLH
Propagation Delay Time LOW-to-HIGH Level Output
Clear to Q
25
ns
t
PHL
Propagation Delay Time HIGH-to-LOW Level Output
Clock to Q or Q
40
ns
t
PLH
Propagation Delay Time LOW-to-HIGH Level Output
Clock to Q or Q
25
ns
3
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DM7473 Dual
Mast
er-
S
l
ave J-K Fl
ip-
F
lops wit
h
Cl
ear and Com
p
l
e
mentar
y
Out
puts
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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