2000 Fairchild Semiconductor Corporation
DS006112
www.fairchildsemi.com
September 1986
Revised February 2000
DM74ALS174
DM74ALS175
Hex/
Q
u
a
d
D-
T
y
pe Fl
ip-
F
l
ops wi
th
Clear
DM74ALS174 DM74ALS175
Hex/Quad D-Type Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. Both have an asynchro-
nous clear input, and the quad (DM74ALS175) version fea-
tures complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
s
Advanced oxide-isolated ion-implanted Schottky TTL
process
s
Pin and functional compatible with LS family counterpart
s
Typical clock frequency maximum is 80 MHz
s
Switching performance guaranteed over full temperature
and V
CC
supply range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
DM74ALS174
DM74ALS175
Ordering Code
Package Number
Package Description
DM74ALS174M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS174N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74ALS175M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
D
M
74ALS174
D
M
74ALS175
Function Table
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Don't Care
=
Transition from LOW-to-HIGH Level
Q
0
=
the level of Q before the indicated steady-state input conditions were established
Note 1: applies to DM74ALS175 only
Logic Diagrams
DM74ALS174
DM74ALS175
Inputs
Outputs
Clear
Clock
D
Q
Q (Note 1)
L
X
X
L
H
H
H
H
L
H
L
L
H
H
L
X
Q
0
Q
0
3
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DM74ALS174
DM74ALS175
Absolute Maximum Ratings
(Note 2)
Note 2: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 3: The symbol
indicates that the rising edge of the clock is used as reference.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
77.9
C/W
M Package
107.3
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
0.4
mA
I
OL
LOW Level Output Current
8
mA
t
W
Pulse Width
Clock
10
HIGH or LOW
ns
Clear LOW
10
t
SETUP
Setup Time (Note 3)
Data Input
10
Clear
6
ns
Inactive State
t
HOLD
Data Hold Time (Note 3)
0
ns
f
CLOCK
Clock Frequency
0
50
MHz
T
A
Free Air Operating Temperature
0
70
C
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4
D
M
74ALS174
D
M
74ALS175
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
C.
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
4.5V, I
IN
=
-
18 mA
-
1.5
V
V
OH
HIGH Level
I
OH
=
-
400
A
V
CC
-
2
V
CC
-
1.6
V
Output Voltage
V
CC
=
4.5V to 5.5V
V
OL
LOW Level
V
CC
=
4.5V
I
OL
=
8 mA
0.35
0.5
V
Output Voltage
I
I
Input Current at
V
CC
=
5.5V, V
IN
=
7V
0.1
mA
Max Input Voltage
I
IH
HIGH Level Input Current
V
CC
=
5.5V, V
IH
=
2.7V
20
A
I
IL
LOW Level Input Current
V
CC
=
5.5V, V
IN
=
0.4V
-
0.1
mA
I
O
Output Drive Current
V
CC
=
5.5V, V
O
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
5.5V
DM74ALS174
11
19
Clock
=
4.5V
mA
Clear
=
GND
DM74ALS175
8
14
D Input
=
GND
Symbol
Parameter
Conditions
Min
Max
Units
f
MAX
Maximum Clock Frequency
R
L
=
500
50
MHz
t
PLH
Propagation Delay Time
C
L
=
50 pF
LOW-to-HIGH Level
V
CC
=
4.5V to 5.5V
5
18
ns
Output From Clear (175 Only)
t
PHL
Propagation Delay Time
HIGH-to-LOW Level
8
23
ns
Output From Clear
t
PLH
Propagation Delay Time
LOW-to-HIGH Level
3
15
ns
Output From Clock
t
PHL
Propagation Delay Time
HIGH-to-LOW Level
5
17
ns
Output From Clock
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