2000 Fairchild Semiconductor Corporation
DS009304
www.fairchildsemi.com
March 1987
Revised February 2000
DM74ALS645A Octal
Bus T
r
ansceiv
e
rs
DM74ALS645A
Octal Bus Transceivers
General Description
These octal bus transceivers are designed for asynchro-
nous two-way communication between data busses. These
devices transmit data from the A bus to the B bus or from
the B bus to the A bus depending upon the level at the
direction control (DIR) input. The enable input (G) can be
used to disable the device so the busses are effectively
isolated.
Features
s
Advanced Oxide-isolated Ion-implanted Schottky TTL
process
s
Switching performance is guaranteed over full tempera-
ture and V
CC
supply range
s
Switching performance specified at 50 pF
s
PNP input design reduces input loading
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
L
=
LOW Logic Level
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
Logic Diagram
Order Number
Package Number
Package Description
DM74ALS645AWM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS645AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Control
Inputs
Operation
G
DIR
L
L
B Data to A Bus
L
H
A Data to B Bus
H
X
Isolation
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2
DM
74ALS64
5A
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
Over Recommended Free Air Temperature Range
Note 2: For I/O ports, I
IH
and I
IL
parameters include the 3-STATE output current (I
OZL
and I
OZH
).
Switching Characteristics
Over Recommended Operating Free Air Temperature Range
Supply Voltage
7V
Input Voltage;
Control Inputs
7V
I/O Ports
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
53.0
C/W
M Package
72.0
C/W
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
15
mA
I
OL
LOW Level Output Current
24
mA
T
A
Operating Free Air Temperature Range
0
70
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
IC
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.5
V
V
OH
HIGH Level Output Voltage
V
CC
=
4.5 to 5.5V
I
OH
=
-
0.4 mA
V
CC
-
2
V
CC
=
Max
I
OH
=
-
3 mA
2.4
3.2
V
I
OH
=
Max
2
V
OL
LOW Level Output Voltage
V
CC
=
Min
I
OL
=
12 mA
0.25
0.4
V
I
OL
=
24 mA
0.35
0.5
I
I
Input Current at
V
CC
=
Max
I/O Ports, V
I
=
5.5V
100
A
Maximum Input Voltage
Control Inputs, V
I
=
7V
100
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V (Note 2)
20
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.4V (Note 2)
-
100
A
I
O
Output Drive Current
V
CC
=
Max, V
O
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
Max
Outputs HIGH
30
45
Outputs LOW
36
55
mA
Outputs Disabled
38
58
Symbol
Parameter
From
To
Conditions
Min
Max
Units
(Input)
(Output)
t
PLH
Propagation Delay Time
A or B
B or A
V
CC
=
4.5 to 5.5V,
3
10
ns
LOW-to-HIGH Level Output
C
L
=
50 pF,
t
PHL
Propagation Delay Time
A or B
B or A
R1
=
R2
=
500
3
10
ns
HIGH-to-LOW Level Output
t
PZH
Output Enable Time to HIGH Level Output
G
A or B
5
20
ns
t
PZL
Output Enable Time to LOW Level Output
G
A or B
5
20
ns
t
PHZ
Output Disable Time from HIGH Level Output
G
A or B
2
10
ns
t
PLZ
Output Disable Time from LOW Level Output
G
A or B
4
15
ns
3
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DM74ALS645A
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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4
DM
7
4
ALS645A Oct
a
l
Bus T
r
anscei
vers
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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