2000 Fairchild Semiconductor Corporation
DS009174
www.fairchildsemi.com
October 1986
Revised March 2000
DM74ALS652 Octal
3-ST
A
T
E
Bus T
r
ansc
eiver
and
Regi
ster
DM74ALS652
Octal 3-STATE Bus Transceiver and Register
General Description
This device incorporates an octal transceiver and an octal
D-type register configured to enable transmission of data
from bus to bus or internal register to bus.
This bus transceiver features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high level logic drive provide this device with the
capability of being connected directly to and driving the bus
lines in a bus organized system without need for interface
or pull-up components. They are particularly attractive for
implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The registers in the DM74ALS652 are edge-triggered D-
type flip-flops. On the positive transition of the clock (CAB
or CBA), the input data is stored into the appropriate regis-
ter. The CAB input controls the transfer of data into the A
register and the CBA input controls the B register.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data and a HIGH level selects
stored data. The select controls have a "make before
break" configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between stored and real-time data.
The enable (GAB and GBA) control pins provide four
modes of operation: real-time data transfer from bus A to
B, real-time data transfer from bus B to A, real-time bus A
and/or B data transfer to internal storage, or internal stored
data transfer to bus A and/or B.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
3-STATE buffer-type outputs drive bus lines directly
s
Independent registers and enables for A and B buses
s
Multiplexed real-time and stored data
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Order Number
Package Number Package Description
DM74ALS652WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS652NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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2
D
M
74ALS652
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don't Care (Either LOW or HIGH Logic Levels, including transitions)
H/L
=
Either LOW or HIGH Logic Level excluding transitions
=
Positive-going edge of pulse
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Note 2: Select control
=
L; clocks can occur simultaneously
Select control
=
H; clocks must be staggered in order to load both registers.
Logic Diagram
Inputs
Data I/O (Note 1)
Operation or Function
GAB
GBA
CAB
CBA
SAB
SBA
A1 thru A8
B1 thru B8
X
H
H/L
X
X
Input
Not Specified Store A, Hold B
L
X
H/L
X
X
Not Specified
Input
Store B, Hold A
L
H
X
X
Input
Input
Store A and B Data
L
H
H/L
H/L
X
X
Input
Input
Isolation, Hold Storage
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H/L
X
H
Output
Input
Stored B Data to A Bus
H
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
H
H
X
X
Input
Output
Stored A Data to B Bus
H
H
X
(Note 2)
X
Input
Output
Store A in both Registers
L
L
X
X
(Note 2)
Output
Input
Store B in both Registers
H
L
H or L
H or L
H
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
3
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DM74ALS652
Absolute Maximum Ratings
(Note 3)
Note 3: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 4:
=
with reference to the LOW-to-HIGH transition of the respective clock.
Electrical Characteristics
over recommended free air temperature range
Note 5: For I/O ports the 3-STATE output currents (I
OZH
and I
OZL
) are included in the I
IH
and I
IL
parameters.
Supply Voltage
7V
Input Voltage
Control Inputs
7V
I/O Ports
5.5V
Operating Free-Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
44.5
C/W
M Package
80.5
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
15
mA
I
OL
LOW Level Output Current
24
mA
f
CLK
Clock Frequency
0
40
MHz
t
W
Pulse Duration, Clocks Low or High
12.5
ns
t
SU
Data Setup Time, A before CAB or
10
ns
B before CBA (Note 4)
t
H
Data Hold Time, A after CAB or
0
ns
B after CBA (Note 4)
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
4.5V to 5.5V
I
OH
=
-
0.4 mA
V
CC
-
2
Output Voltage
V
CC
=
Min
I
OH
=
-
3 mA
2.4
3.2
V
I
OH
=
Max
2
V
OL
LOW Level
V
CC
=
Min
I
OL
=
12 mA
0.25
0.4
Output Voltage
I
OL
=
24 mA
0.35
0.5
V
I
OL
=
48 mA
0.35
0.5
I
I
Input Current at Maximum
V
CC
=
Max
I/O Ports, V
I
=
5.5V
100
A
Input Voltage
Control Inputs, V
I
=
7V
100
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V, (Note 5)
20
A
I
IL
LOW Level
V
CC
=
Max,
Control Inputs
-
200
A
Input Current
V
I
=
0.4V (Note 5)
I/O Ports
-
200
I
O
Output Drive Current
V
CC
=
Max, V
O
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
Max
Outputs HIGH
47
76
Outputs LOW
55
88
mA
Outputs Disabled
55
88
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4
D
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74ALS652
Switching Characteristics
over recommended operating free air temperature range
(Note 6)
Note 6: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Symbol
Parameter
Conditions
From (Input)
Min
Max
Units
To (Output)
t
PLH
Propagation Delay Time
V
CC
=
4.5V to 5.5V,
CBA or CAB
10
30
ns
LOW-to-HIGH Level Output
C
L
=
50 pF,
to A or B
t
PHL
Propagation Delay Time
R
1
=
R
2
=
500
,
CBA or CAB
5
17
ns
HIGH-to-LOW Level Output
T
A
=
Min to Max
to A or B
t
PLH
Propagation Delay Time
A or B to
5
18
ns
LOW-to-HIGH Level Output
B or A
t
PHL
Propagation Delay Time
A or B to
3
12
ns
HIGH-to-LOW Level Output
B or A
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
SBA or SAB
12
35
ns
(with A or B LOW) (Note 6)
to A or B
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
SBA or SAB
6
20
ns
(with A or B LOW) (Note 6)
to A or B
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
SBA or SAB
6
25
ns
(with A or B HIGH) (Note 6)
to A or B
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
SBA or SAB
5
20
ns
(with A or B HIGH) (Note 6)
to A or B
t
PZH
Output Enable Time
GBA to
3
17
ns
to HIGH Level Output
A
t
PZL
Output Enable Time
GBA to
5
18
ns
to LOW Level Output
A
t
PHZ
Output Disable Time
GBA to
1
10
ns
from HIGH Level Output
A
t
PLZ
Output Disable Time
GBA to
2
16
ns
from LOW Level Output
A
t
PZH
Output Enable Time
GAB to
6
22
ns
to HIGH Level Output
B
t
PZL
Output Enable Time
GAB to
6
18
ns
to LOW Level Output
B
t
PHZ
Output Disable Time
GAB to
1
10
ns
from HIGH Level Output
B
t
PLZ
Output Disable Time
GAB to
2
16
ns
from LOW Level Output
B
5
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DM74ALS652
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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