2000 Fairchild Semiconductor Corporation
DS006291
www.fairchildsemi.com
April 1984
Revised March 2000
DM74AS161
DM74AS163 Synchr
onous
4-
Bit
C
o
u
n
ter
wit
h
A
s
ynchronous
Cl
ear
Synchr
onous 4-Bi
t Counter
DM74AS161 DM74AS163
Synchronous 4-Bit Counter with Asynchronous Clear
Synchronous 4-Bit Counter
General Description
These synchronous presettable counters feature an inter-
nal carry look ahead for application in high speed counting
designs. The DM74AS161 and DM74AS163 are 4-bit
binary counters. The DM74AS161 clear asynchronously,
while the DM74AS163 clear synchronously. The carry out-
put is decoded to prevent spikes during normal counting
mode of operation. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that outputs
change coincident with each other when so instructed by
count enable inputs and internal gating. This mode of oper-
ation eliminates the output counting spikes which are nor-
mally associated with asynchronous (ripple clock)
counters. A buffered clock input triggers the four flip-flops
on the rising (positive-going) edge of the clock input wave-
form.
These counters are fully programmable, that is, the outputs
may each be preset to either level. As presetting is syn-
chronous, setting up a low level at the LOAD input disables
the counter and causes the outputs to agree with set up
data after the next clock pulse regardless of the levels of
enable input. LOW-to-HIGH transitions at the LOAD input
are perfectly acceptable regardless of the logic levels on
the clock or enable inputs.
The DM74AS161 clear function is asynchronous. A low
level at the clear input sets all four of the flip-flop outputs
LOW regardless of the levels of clock, load or enable
inputs. This counter is provided with a clear on power-up
feature. The DM74AS163 clear function is synchronous;
and a low level at the clear input sets all four of the flip-flop
outputs LOW after the next clock pulse, regardless of the
levels of enable inputs. This synchronous clear allows the
count length to be modified easily, as decoding the maxi-
mum count desired can be accomplished with one external
NAND gate. The gate output is connected to the clear input
to synchronously clear the counter to all LOW outputs.
LOW-to-HIGH transitions at the clear input of the
DM74AS163 is also permissible regardless of the levels of
logic on the clock, enable or load inputs.
The carry look ahead circuitry provides for cascading
counters for n bit synchronous application without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs (P and T) and a ripple carry
output. Both count-enable inputs must be HIGH to count.
The T input is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high
level output pulse with a duration approximately equal to
the high level portion of QA output. This high level overflow
ripple carry pulse can be used to enable successive cas-
caded stages. HIGH-to-LOW level transitions at the enable
P or T inputs of the DM74AS161 and DM74AS163, may
occur regardless of the logic level on the clock.
The DM74AS161 and DM74AS163 feature a fully indepen-
dent clock circuit. Changes made to control inputs (enable
P or T, or load) that will modify the operating mode will
have no effect until clocking occurs. The function of the
counter (whether enabled, disabled, loading or counting)
will be dictated solely by the conditions meeting the stable
set-up and hold times.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
s
Improved AC performance over Schottky and low power
Schottky counterparts
s
Synchronously programmable
s
Internal look ahead for fast counting
s
Carry output for n-bit cascading
s
Synchronous counting
s
Load control line
s
ESD inputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package Number
Package Description
DM74AS161M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS161N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74AS163M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS163N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com
4
DM
74AS161
DM
74AS163
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
71.5
C/W
M Package
101.0
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
2
mA
I
OL
LOW Level Output Current
20
mA
f
CLK
Clock Frequency
0
75
MHz
t
SU
t
SETUP
, Set-Up Time
Data; A, B, C, D
8
ns
En P, En T
8
ns
LOAD
8
ns
CLEAR (Only for
LOW
12
ns
DM74AS163)
HIGH
9
Set-up 1
CLEAR
8
ns
(Only for DM74AS161)
t
H
t
HOLD
, Hold Time
Data; A, B, C, D
0
ns
En P, En T
0
ns
LOAD
0
ns
CLEAR (Only for DM74AS163)
0
ns
Hold 0
CLEAR
0
ns
(Only for DM74AS161)
t
WCLK
Width of Clock Pulse
6.7
ns
t
WCLR
Width of Clear Pulse, (DM74ASAS161 LOW)
8
ns
5
www.fairchildsemi.com
DM74AS161
DM74AS163
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
C
Note 2: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, I
OS
.
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
4.5V, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
I
OH
=
-
2 mA,
V
CC
-
2
V
Output Voltage
V
CC
=
4.5 to 5.5V
V
OL
LOW
Level V
CC
=
4.5V,
0.35
0.5
V
Output Voltage
I
OL
=
20 mA
I
I
Input Current @ Max
V
CC
=
5.5V,
LOAD
0.3
Input Voltage
V
IH
=
7V
ENT
0.2
mA
Others
0.1
I
IH
HIGH Level Input Current
V
CC
=
5.5V,
LOAD
60
V
IH
=
2.7V
ENT
40
A
Others
20
I
IL
LOW Level Input Current
V
CC
=
5.5V,
LOAD
-
0.5
V
IL
=
0.4V
ENT
-
1
mA
Others
-
0.5
I
O
(Note 2)
Output Drive Current
V
CC
=
5.5V, V
O
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
5.5V
35
53
mA
Symbol
Parameter
Conditions
From
To
Min
Max
Units
f
MAX
Maximum Clock Frequency
V
CC
=
4.5V to 5.5V
75
MHz
t
PHL
Propagation Delay Time
R
L
=
500
Clock
Ripple Carry
2
12.5
ns
HIGH-to-LOW Level Output
C
L
=
50 pF
t
PLH
Propagation Delay Time
Clock
Ripple Carry
1
8
ns
LOW-to-HIGH Level Output
with Load HIGH
t
PLH
Propagation Delay Time
Clock
Ripple Carry
3
16.5
ns
LOW-to-HIGH Level Output
with Load LOW
t
PLH
Propagation Delay Time
Clock
Any Q
1
7
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock
Any Q
2
13
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
En T
Ripple Carry
1.5
9
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
En T
Ripple Carry
1
8.5
ns
HIGH-to-LOW Level Output
t
PHL
Propagation Delay Time
CLEAR
Any Q
2
13
ns
HIGH-to-LOW Level Output
(DM74AS161)
t
PHL
Propagation Delay Time
CLEAR
Ripple Carry
2
12.5
ns
HIGH-to-LOW Level Output
(DM74AS161)
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