2000 Fairchild Semiconductor Corporation
DS006299
www.fairchildsemi.com
October 1986
Revised February 2000
DM74AS245
Octal
Bus
T
r
anscei
ver
w
i
th
3-
ST
A
T
E
O
u
tput
s
DM74AS245
Octal Bus Transceiver with 3-STATE Outputs
General Description
This advanced Schottky device contains 8 pairs of
3-STATE logic elements configured as octal bus transceiv-
ers. These circuits are designed for use in memory, micro-
processor systems and in asynchronous bidirectional data
buses. Two way communication between buses is con-
trolled by the (DIR) input. Data transmits either from the A
bus to the B bus or from the B bus to the A bus. Both the
driver and receiver outputs can be disabled via the (G)
enable input which causes outputs to enter the high imped-
ance mode so that the buses are effectively isolated.
Features
s
Advanced oxide-isolated, ion-implanted Schottky
TTL process
s
Non-inverting logic output
s
3-STATE outputs independently controlled on
A and B buses
s
Low output impedance to drive terminated transmission
lines to 133
s
Switching response specified into 500
/50 pF
s
Specified to interface with CMOS at V
OH
=
V
CC
-
2V
s
PNP inputs reduce input loading
s
Switching specifications guaranteed over full
temperature and V
CC
range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
Order Number
Package Number
Package Description
DM74AS245WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS245SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74AS245N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Control
Inputs
Operation
G
DIR
L
L
B Data to A Bus
L
H
A Data to B Bus
H
X
Hi-Z
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2
DM
74AS245
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range
Switching Characteristics
over recommended operating free air temperature range
Supply Voltage, V
CC
7V
Input Voltage
Control Inputs
7V
I/O Ports
5.5V
Operating Free Air Temperature Range
0
C to 70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
51.5
C/W
M Package
76.0
C/W
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
15
mA
I
OL
LOW Level Output Current
48
mA
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
4.5V, I
IN
=
-
18 mA
-
1.2
V
V
OH
HIGH Level Output
V
CC
=
4.5V, I
OH
=
-
3 mA
2.4
3.2
Voltage
V
CC
=
4.5V, I
OH
=
-
15 mA
2
2.3
V
I
OH
=
-
2 mA, V
CC
=
4.5V to 5.5V
V
CC
-
2
V
OL
LOW Level Output Voltage
V
CC
=
4.5V, I
OL
=
Max
0.35
0.55
V
I
I
Input Current at Max
V
CC
=
5.5V, V
IN
=
7V,
0.1
mA
Input Voltage
(V
IN
=
5.5V for A or B Ports)
I
IH
HIGH Level Input Current
V
CC
=
5.5V,
Control Inputs
20
A
V
IN
=
2.7V
A or B Ports
70
I
IL
LOW Level Input Current
V
CC
=
5.5V,
Control Inputs
-
0.5
mA
V
IN
=
0.4V
A or B Ports
-
0.75
I
O
Output Drive Current
V
CC
=
5.5V, V
OUT
=
2.25V
-
50
-
150
mA
I
CC
Supply Current
V
CC
=
5.5V
Output HIGH
62
97
Output LOW
95
149
mA
3-STATE
79
123
Symbol
Parameter
Conditions
From
To
Min
Max
Units
t
PLH
Propagation Delay Time
V
CC
=
4.5V to 5.5V,
A or B
B or A
2
7.5
ns
HIGH-to-LOW Level Output
R
1
=
R
2
=
500
,
t
PHL
Propagation Delay Time
C
L
=
50 pF
A or B
B or A
2
7
ns
HIGH-to-LOW Level Output
t
PZL
Output Enable Time to LOW Level
G
A or B
2
8.5
ns
t
PZH
Output Enable Time to HIGH Level
G
A or B
2
9
ns
t
PLZ
Output Disable Time from LOW Level
G
A or B
2
9.5
ns
t
PHZ
Output Disable Time from HIGH Level
G
A or B
2
5.5
ns
3
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DM74AS245
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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4
DM
74AS245
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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DM74AS245
Octal
Bus
T
r
anscei
ver
w
i
th
3-
ST
A
T
E
O
u
tput
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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