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Электронный компонент: DM74AS646NT

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2000 Fairchild Semiconductor Corporation
DS006324
www.fairchildsemi.com
October 1986
Revised March 2000
DM74AS646
DM74AS648
Octal
Bus
T
r
anscei
ver
and Regi
st
er
DM74AS646 DM74AS648
Octal Bus Transceiver and Register
General Description
This device incorporates an octal bus transceiver and an
octal D-type register configured to enable multiplexed
transmission of data from bus to bus or internal register to
bus.
This bus transceiver features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance third
state and increased high-logic-level drive provide this
device with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. It is particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The registers in the DM74AS646, DM74AS648 are edge-
triggered D-type flip-flops. On the positive transition of the
clock (CAB or CBA), the input bus data is stored.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data, and a HIGH level selects
stored data. The select controls have a "make before
break" configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between stored and real-time data.
The enable G and direction control pins provide four modes
of operation; real-time data transfer from bus A to B, real-
time data transfer from bus B to A, real-time bus A and/or B
data transfer to internal storage, or internal store data
transfer to bus A or B.
When the enable G pin is LOW, the direction pin selects
which bus receives data. When the enable G pin is HIGH,
both buses become disabled yet their input function is still
enabled.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally and pin-for-pin compatible with LS TTL
counterpart
s
3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package Number
Package Description
DM74AS646WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS646NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
DM74AS648WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS648NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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2
DM
74AS646

DM
74AS648
Connection Diagram
Function Table
H--HIGH level; L--LOW level; X--irrelevant;
--LOW-to-HIGH level transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Inputs
Data I/O (Note 1)
Operation or Function
G
DIR
CAB
CBA
SAB SBA A1 thru A8 B1 thru B8
DM74AS646
DM74AS648
H
X
H or L H or L
X
X
Input
Input
Isolation, Hold Storage
Isolation, Hold Storage
X
X
X
Store A and B Data
Store A and B Data
L
L
X
X
X
L
Output
Input
Real Time B Data to A Bus
Real Time B Data to A Bus
L
X
H or L
X
H
Stored B Data to A Bus
Stored B Data to A Bus
L
H
X
X
L
X
Input
Output
Real Time A Data to B Bus
Real Time A Data to B Bus
H
H or L
X
H
X
Stored A Data to B Bus
Stored A Data to B Bus
X
X
X
X
X
Input
Unspecified
(Note 1)
Store A, B Unspecified
(Note 1)
Store A, B Unspecified
(Note 1)
X
X
X
X
X
Unspecified
(Note 1)
Input
Store B, A Unspecified
(Note 1)
Store B, A Unspecified
(Note 1)
3
www.fairchildsemi.com
DM74AS646
DM74AS648
Logic Diagrams
(positive logic)
DM74AS646
DM74AS648
Different Modes of Control for DM74AS646, DM74AS648
Storage From A, B or A and B
Transfer Stored Data to A or B
(Note 2)
Real-Time Transfer Bus A to Bus B
(Note 2)
Real-Time Transfer Bus B to Bus A
(Note 2)
Note 2: The complement of A and B data are stored and transferred for DM74AS648
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4
DM
74AS646

DM
74AS648
Absolute Maximum Ratings
(Note 3)
Note 3: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 4: The (
) arrow indicates the positive edge of the Clock is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
C.
Note 5: For I/O ports, the parameters I
IH
and I
IL
include the OFF-State current, I
OZH
and I
OZL
.
Supply Voltage
7V
Input Voltage
Control Inputs
7V
I/O Ports
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
41.1
C/W
M Package
81.5
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
15
mA
I
OL
LOW Level Output Current
48
mA
f
CLK
Clock Frequency
0
90
MHz
t
W
Width of Clock Pulse
HIGH
5
ns
LOW
6
ns
t
SU
Data Setup Time (Note 4)
6
ns
t
H
Data Hold Time (Note 4)
0
ns
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
4.5V, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
4.5V, V
IL
=
Max
I
OH
=
Max
2
Output Voltage
V
IH
=
Min
I
OH
=
-
3 mA
2.4
3.2
V
V
CC
=
4.5V to 5.5V, I
OH
=
-
2 mA
V
CC
-
2
V
OL
LOW
Level V
CC
=
4.5V, V
IL
=
Min
0.35
0.5
V
Output Voltage
V
IH
=
2V, I
OL
=
Max
I
I
Input Current @ Max
V
CC
=
5.5V
V
I
=
7V
Control Inputs
0.1
mA
Input Voltage
V
I
=
5.5V
A or B Ports
0.1
I
IH
HIGH Level Input Current
V
CC
=
5.5V, V
IH
=
2.7V
Control Inputs
20
A
(Note 5)
A or B Ports
70
I
IL
LOW Level Input Current
V
CC
=
5.5V, V
IL
=
0.4V
Control Inputs
-
0.5
mA
(Note 5)
A or B Ports
-
0.75
I
O
Output Drive Current
V
CC
=
5.5V, V
O
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
5.5V
Outputs HIGH
120
195
DM74AS646
Outputs LOW
130
211
Outputs Disabled
130
211
mA
Outputs HIGH
110
185
DM74AS648
Outputs LOW
120
195
Outputs Disabled
120
195
5
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DM74AS646
DM74AS648
DM74AS646 Switching Characteristics
Note 6: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Symbol
Parameter
Conditions
From
To
Min
Max
Units
(Input)
(Output)
f
MAX
Maximum Clock
V
CC
=
4.5V to 5.5V,
90
MHz
Frequency
R
1
=
R
2
=
500
t
PLH
Propagation Delay Time
C
L
=
50 pF
2
8.5
ns
LOW-to-HIGH Level Output
CBA or CAB
A or B
t
PHL
Propagation Delay Time
2
9
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
2
9
ns
LOW-to-HIGH Level Output
A or B
B or A
t
PHL
Propagation Delay Time
1
7
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
2
11
ns
LOW-to-HIGH Level Output
SBA or SAB
A or B
t
PHL
Propagation Delay Time
2
9
ns
HIGH-to-LOW Level Output
(Note 6)
t
PZH
Output Enable Time
2
9
ns
to HIGH Level Output
t
PZL
Output Enable Time
3
14
ns
to LOW Level Output
Enable G
A or B
t
PHZ
Output Disable Time
2
9
ns
from HIGH Level Output
t
PLZ
Output Disable Time
2
9
ns
from LOW Level Output
t
PZH
Output Enable Time
3
16
ns
to HIGH Level Output
t
PZL
Output Enable Time
3
18
ns
to LOW Level Output
DIR
A or B
t
PHZ
Output Disable Time
2
10
ns
from HIGH Level Output
t
PLZ
Output Disable Time
2
10
ns
from LOW Level Output