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Электронный компонент: DM74AS651WM

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2003 Fairchild Semiconductor Corporation
DS006325
www.fairchildsemi.com
October 1986
Revised July 2003
DM74AS651
DM74AS652
Octal
Bus
T
r
anscei
ver
and Regi
st
er
DM74AS651 DM74AS652
Octal Bus Transceiver and Register
General Description
These devices incorporate an octal transceiver and an
octal D-type register configured to enable transmission of
data from bus to bus or internal register to bus. The
DM74AS651 offers 64-Industrial grade product guarantee-
ing performance from
-
40
C to
+
85
C.
These bus transceivers feature totem-pole 3-STATE out-
puts designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these devices
with the capability of being connected directly to and driv-
ing the bus lines in a bus-organized system without need
for interface or pull-up components. They are particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The registers in the DM74AS651 and DM74AS652 are
edge-triggered D-type flip-flops. On the positive transition
of the clock (CAB or CBA), the input data is stored.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data and a HIGH level selects
stored data. The select controls have a "make before
break" configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between stored and real-time data.
The Enable (GAB and GBA) control pins provide four
modes of operation; real-time data transfer from bus A-to-
B, real-time data transfer from bus B-to-A, real-time bus A
and/or B data transfer to internal storage, or internal stored
data transfer to bus A and/or B.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
3-STATE buffer-type outputs drive bus lines directly
s
Guaranteed performance over industrial temperature
range (
-
40
C to
+
85
C) in 64-grade products
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package Number
Package Description
DM74AS651WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
DM74AS651NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DM74AS652WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
DM74AS652NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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2
DM
74AS651


DM
74AS652
Connection Diagram
Function Table
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
=
LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Note 2: If the select control is LOW, the clocks can occur simultaneously. If the select control is HIGH, the clocks must be staggered in order to load both
registers.
INPUTS
DATA I/O (Note 1)
OPERATION OR FUNCTION
GAB GBA
CAB
CBA
SAB
SBA
A1 B1 DM74AS651
DM74AS652
THRU
THRU
A8
B8
L
H
H or L H or L
X
X
Input
Input
Isolation
Isolation
L
H
X
X
Store A and B Data
Store A and B Data
L
L
X
X
X
L
Output
Input
Real Time B Data to A
Bus
Real Time B Data to A
Bus
L
L
X
H or L
X
H
Stored B Data to A Bus
Stored B Data to A Bus
H
H
X
X
L
X
Input
Output
Real Time A Data to B
Bus
Real Time A Data to B
Bus
H
H
H or L
X
H
X
Stored A Data to B Bus
Stored A Data to B Bus
H
L
H or L H or L
H
H
Output
Output
Stored A Data to B Bus
Stored A Data to B Bus
& Stored B Data to A Bus & Stored B Data to A Bus
X
H
H or L
X
X
Input
Unspecified
(Note 1)
Store A, Hold B
Store A, Hold B
H
H
X
(Note
2)
X
Input
Output
Store A in both registers
Store A in both registers
L
X
H or L
X
X
Unspecified
(Note 1)
Input
Hold A, Store B
Hold A, Store B
L
L
X
X
(Note
2)
Output
Input
Store B in both registers
Store B in both registers
3
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DM74AS651

DM74AS652
Logic Diagrams
DM74AS651
DM74AS652
Schematics of Inputs and Outputs
Equivalent of All Other Inputs
Typical of All DM74AS651, DM74AS652 Outputs
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4
DM
74AS651


DM
74AS652
Absolute Maximum Ratings
(Note 3)
Note 3: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
C.
Supply Voltage
7V
Input Voltage
Control Inputs
7V
I/O Ports
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
41.1
C/W
M Package
81.5
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
15
mA
I
OL
LOW Level Output Current
48
mA
f
CLK
Clock Frequency
0
90
MHz
t
WCLK
Width of Enable Pulse
HIGH
5
ns
LOW
6
t
SU
Data Setup Time
6
ns
t
H
Data Hold Time
0
ns
T
A
Operating Free Air Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
4.5V, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
4.5V
I
OH
=
Max
2
Output Voltage
I
OH
=
-
3 mA
2.4
3.2
V
V
CC
=
4.5V to 5.5V
I
OH
=
-
2 mA
V
CC
-
2
V
OL
LOW Level Output Voltage
V
CC
=
4.5V, I
OL
=
Max
0.35
0.5
V
I
I
Input Current at
V
CC
=
5.5V
V
I
=
7V
Control Inputs
0.1
mA
Max Input Voltage
V
I
=
5.5V
A or B Ports
0.1
I
IH
HIGH Level
V
CC
=
5.5V,
Control Inputs
20
A
Input Current
V
IH
=
2.7V
A or B Ports
70
I
IL
LOW Level
V
CC
=
5.5V,
Control Inputs
-
0.5
mA
Input Current
V
IL
=
0.4V
A or B Ports
-
0.75
I
O
Output Drive Current
V
CC
=
5.5V, V
O
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
5.5V
Outputs HIGH
110
185
mA
DM74AS651
Outputs LOW
120
195
Outputs Disabled
130
195
Outputs HIGH
120
195
DM74AS652
Outputs LOW
130
211
Outputs Disabled
130
211
5
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DM74AS651

DM74AS652
DM74AS651 Switching Characteristics
Note 4: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Symbol
Parameter
Conditions
From
To
Min
Max
Units
f
MAX
Maximum Clock Frequency
V
CC
=
4.5V to 5.5V
90
MHz
t
PLH
Propagation Delay Time
R
1
=
R
2
=
500
2
8.5
ns
LOW-to-HIGH Level Output
C
L
=
50 pF
CBA or CAB
A or B
t
PHL
Propagation Delay Time
2
9
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
2
8
ns
LOW-to-HIGH Level Output
A or B
B or A
t
PHL
Propagation Delay Time
1
7
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
2
11
ns
LOW-to-HIGH Level Output
SBA or SAB
A or B
t
PHL
Propagation Delay Time
(Note 4)
2
9
ns
HIGH-to-LOW Level Output
t
PZH
Output Enable Time
2
10
ns
to HIGH Level Output
t
PZL
Output Enable Time
3
16
ns
to LOW Level Output
Enable GBA
A
t
PHZ
Output Disable Time
2
9
ns
from HIGH Level Output
t
PLZ
Output Disable Time
2
9
ns
from LOW Level Output
t
PZH
Output Disable Time
3
11
ns
to HIGH Level Output
t
PZL
Output Disable Time
3
16
ns
to LOW Level Output
Enable GAB
B
t
PHZ
Output Disable Time
2
10
ns
from HIGH Level Output
t
PLZ
Output Disable Time
2
11
ns
from LOW Level Output