2000 Fairchild Semiconductor Corporation
DS006409
www.fairchildsemi.com
August 1986
Revised April 2000
DM74LS221
Dual
Non-
Retr
igger
a
ble
One-
S
h
ot
w
i
th
Cl
ear
and Compl
e
m
e
nt
ary
Outpu
t
s
DM74LS221 Dual Non-Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
The DM74LS221 is a dual monostable multivibrator with
Schmitt-trigger input. Each device has three inputs permit-
ting the choice of either leading-edge or trailing-edge trig-
gering. Pin (A) is an active-LOW trigger transition input and
pin (B) is an active-HIGH transition Schmitt-trigger input
that allows jitter free triggering for inputs with transition
rates as slow as 1 volt/second. This provides the input with
excellent noise immunity. Additionally an internal latching
circuit at the input stage also provides a high immunity to
V
CC
noise. The clear (CLR) input can terminate the output
pulse at a predetermined time independent of the timing
components. This (CLR) input also serves as a trigger
input when it is pulsed with a low level pulse transition
(
). To obtain the best and trouble free operation from
this device please read operating rules as well as the Fair-
child Semiconductor one-shot application notes carefully
and observe recommendations.
Features
s
A dual, highly stable one-shot
s
Compensated for V
CC
and temperature variations
s
Pin-out identical to DM74LS123 (Note 1)
s
Output pulse width range from 30 ns to 70 seconds
s
Hysteresis provided at (B) input for added noise
immunity
s
Direct reset terminates output pulse
s
Triggerable from CLEAR input
s
DTL, TTL compatible
s
Input clamp diodes
Note 1: The pin-out is identical to DM74LS123 but, functionally it is not;
refer to Operating Rules #10 in this datasheet.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Can Be Either LOW or HIGH
=
Positive Going Transition
=
Negative Going Transition
=
A Positive Pulse
=
A Negative Pulse
Note 2: This mode of triggering requires first the B input be set from a
LOW-to-HIGH level while the CLEAR input is maintained at logic LOW
level. Then with the B input at logic HIGH level, the CLEAR input whose
positive transition from LOW-to-HIGH will trigger an output pulse.
Order Number
Package Number
Package Description
DM74LS221M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS221SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS221N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
CLEAR
A
B
Q
Q
L
X
X
L
H
X
H
X
L
H
X
X
L
L
H
H
L
H
H
(Note 2)
L
H
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2
DM74LS221 D
u
a
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Non-Ret
r
i
ggerabl
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ne-
Shot
Functional Description
The basic output pulse width is determined by selection of
an external resistor (R
X
) and capacitor (C
X
). Once trig-
gered, the basic pulse width is independent of further input
transitions and is a function of the timing components, or it
may be reduced or terminated by use of the active low
CLEAR input. Stable output pulse width ranging from 30 ns
to 70 seconds is readily obtainable.
Operating Rules
1. An external resistor (R
X
) and an external capacitor
(C
X
) are required for proper operation. The value of C
X
may vary from 0 to approximately 1000
F. For small
time constants high-grade mica, glass, polypropylene,
polycarbonate, or polystyrene material capacitor may
be used. For large time constants use tantalum or spe-
cial aluminum capacitors. If timing capacitor has leak-
ages approaching 100 nA or if stray capacitance from
either terminal to ground is greater than 50 pF the tim-
ing equations may not represent the pulse width the
device generates.
2. When an electrolytic capacitor is used for C
X
a switch-
ing diode is often required for standard TTL one-shots
to prevent high inverse leakage current. This switching
diode is not needed for the DM74LS221 one-shot and
should not be used.
Furthermore, if a polarized timing capacitor is used on
the DM74LS221, the positive side of the capacitor
should be connected to the "C
EXT
" pin (Figure 1).
3. For C
X
>>
1000 pF, the output pulse width (t
W
) is
defined as follows:
t
W
=
KR
X
C
X
where [R
X
is in k
]
[C
X
is in pF]
[t
W
is in ns]
K
Ln2
=
0.70
4. The multiplicative factor K is plotted as a function of C
X
for design considerations: (See Figure 4).
5. For C
X
<
1000 pF see Figure 3 for t
W
vs. C
X
family
curves with R
X
as a parameter.
6. To obtain variable pulse widths by remote trimming,
the following circuit is recommended: (See Figure 2).
7. Output pulse width versus V
CC
and temperatures: Fig-
ure 5 depicts the relationship between pulse width vari-
ation versus V
CC
. Figure 6 depicts pulse width variation
versus temperatures.
8. Duty cycle is defined as t
W
/T
100 in percentage, if it
goes above 50% the output pulse width will become
shorter. If the duty cycle varies between LOW and
HIGH values, this causes output pulse width to vary, or
jitter (a function of the R
EXT
only). To reduce jitter, R
EXT
should be as large as possible, for example, with
R
EXT
=
100k jitter is not appreciable until the duty cycle
approaches 90%.
9. Under any operating condition C
X
and R
X
must be kept
as close to the one-shot device pins as possible to min-
imize stray capacitance, to reduce noise pick-up, and
to reduce I-R and Ldi/dt voltage developed along their
connecting paths. If the lead length from C
X
to pins (6)
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations.
A non-inductive and low capacitive path is necessary to
ensure complete discharge of C
X
in each cycle of its
operation so that the output pulse width will be accu-
rate.
10. Although the DM74LS221's pin-out is identical to the
DM74LS123 it should be remembered that they are not
functionally identical. The DM74LS123 is a retrigger-
able device such that the output is dependent upon the
input transitions when its output "Q" is at the "High"
state. Furthermore, it is recommended for the
DM74LS123 to externally ground the C
EXT
pin for
improved system performance. However, this pin on
the DM74LS221 is not an internal connection to the
device ground. Hence, if substitution of an DM74LS221
onto an DM74LS123 design layout where the C
EXT
pin
is wired to the ground, the device will not function.
11. V
CC
and ground wiring should conform to good high-
frequency standards and practices so that switching
transients on the V
CC
and ground return leads do not
cause interaction between one-shots. A 0.01
F to 0.10
F bypass capacitor (disk ceramic or monolithic type)
from V
CC
to ground is necessary on each device. Fur-
thermore, the bypass capacitor should be located as
close to the V
CC
-pin as space permits.
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4
DM74LS221 D
u
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Non-Ret
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ne-
Shot
Absolute Maximum Ratings
(Note 3)
Note 3: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 4: T
A
=
25
C and V
CC
=
5V.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
T
+
Positive-Going Input Threshold Voltage
1
2
V
at the A Input (V
CC
=
Min)
V
T
-
Negative-Going Input Threshold Voltage
0.8
1
V
at the A Input (V
CC
=
Min)
V
T
+
Positive-Going Input Threshold Voltage
1
2
V
at the B Input (V
CC
=
Min)
V
T
-
Negative-Going Input Threshold Voltage
0.8
0.9
V
at the B Input (V
CC
=
Min)
I
OH
HIGH Level Output Current
-
0.4
mA
I
OL
LOW Level Output Current
8
mA
t
W
Pulse Width
Data
40
ns
(Note 4)
Clear
40
t
REL
Clear Release Time (Note 4)
15
ns
Rate of Rise or Fall of
1
Schmitt Input (B) (Note 4)
Rate of Rise or Fall of
1
Logic Input (A) (Note 4)
R
EXT
External Timing Resistor (Note 4)
1.4
100
k
C
EXT
External Timing Capacitance (Note 4)
0
1000
F
DC
Duty Cycle
R
T
=
2 k
50
%
(Note 4)
R
T
=
R
EXT
(Max)
60
T
A
Free Air Operating Temperature
0
70
C
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