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Электронный компонент: DM74LS279

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2000 Fairchild Semiconductor Corporation
DS006420
www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS279
Quad
S-R L
a
tch
DM74LS279
Quad S-R Latch
General Description
The DM74LS279 consists of four individual and indepen-
dent Set-Reset Latches with active low inputs. Two of the
four latches have an additional S input ANDed with the pri-
mary S input. A LOW on any S input while the R input is
HIGH will be stored in the latch and appear on the corre-
sponding Q output as a HIGH. A LOW on the R input while
the S input is HIGH will clear the Q output to a LOW. Simul-
taneous transition of the R and S inputs from LOW-to-
HIGH will cause the Q output to be indeterminate. Both
inputs are voltage level triggered and are not affected by
transition time of the input data.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Level
L
=
LOW Level
Q
0
=
The Level of Q before the indicated input conditions were established.
Note 1: For latches with double S inputs:
H
=
both S inputs HIGH
L
=
one or both S inputs LOW
Note 2: This output level is pseudo stable; that is, it may not persist when
the S and R inputs return to their inactive (HIGH) level.
Order Number
Package Number
Package Description
DM74LS279M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS279N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Output
S (Note 1)
R
Q
L
L
H (Note 2)
L
H
H
H
L
L
H
H
Q
0
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2
DM74LS279
Absolute Maximum Ratings
(Note 3)
Note 3: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 4: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 6: I
CC
is measured with all R inputs grounded, all S inputs at 4.5V and all outputs OPEN.
Switching Characteristics
at V
CC
=
5V and T
A
=
25
C
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
0.4
mA
I
OL
LOW Level Output Current
8
mA
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 4)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.5
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.7
3.5
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW
Level V
CC
=
Min, I
OL
=
Max
0.35
0.5
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
I
OL
=
4 mA, V
CC
=
Min
0.25
0.4
I
I
Input Current @ Max Input Voltage
V
CC
=
Max, V
I
=
7V
0.1
mA
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
20
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.4V
-
0.4
mA
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 5)
-
20
-
100
mA
I
CC
Supply Current
V
CC
=
Max (Note 6)
3.8
7
mA
From (Input)
R
L
=
2 k
Symbol
Parameter
To (Output)
C
L
=
15 pF
C
L
=
50 pF
Units
Min
Max
Min
Max
t
PLH
Propagation Delay Time
S to Q
22
25
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
S to Q
15
23
ns
HIGH-to-LOW Level Output
t
PHL
Propagation Delay Time
R to Q
27
33
ns
HIGH-to-LOW Level Output
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3
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DM74LS279
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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4
DM
74
LS279
Quad S-R Latc
h
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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