2000 Fairchild Semiconductor Corporation
DS009056
www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS645
Octa
l
Bus T
r
anscei
ver
DM74LS645
Octal Bus Transceiver
General Description
These octal bus transceivers are designed for asynchro-
nous two-way communication between data buses. The
devices transmit data from the A bus to the B bus or from
the B bus to the A bus depending upon the level at the
direction control (DIR) input. The enable input (G) can be
used to disable the device so that the buses are effectively
isolated.
Features
s
Bi-directional bus transceivers in high-density 20-pin
packages
s
Hysteresis at bus inputs improves noise margins
s
3-STATE outputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
Order Number
Package Number
Package Description
DM74LS645WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS645N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Control
Inputs
DM74LS645
G
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
www.fairchildsemi.com
2
DM74LS645
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: Voltage values are with respect to the network ground terminal.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 3: For conditions shown as Min or Max, use the appropriate value specified under Recommended Operating Conditions.
Note 4: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
55
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage (Note 2)
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.6
V
I
OH
HIGH Level Output Current
-
15
mA
I
OL
LOW Level Output Current
24
mA
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions (Note 3)
Min
Typ
Max
Units
(Note 4)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
18 mA
-
1.5
V
H
YS
Hysteresis (V
T
+
-
V
-
)
V
CC
=
Min
0.2
0.4
V
A or B Input
V
OH
HIGH Level Output Voltage
V
CC
=
Min, V
IH
=
2V,
I
OH
=
-
3 mA
2.4
3.4
V
V
IL
=
Max
I
OH
=
Max
2
V
OL
LOW Level Output Voltage
V
CC
=
Min, V
IH
=
2V,
I
OL
=
12 mA
0.25
0.4
V
V
IL
=
Max
I
OL
=
24 mA
0.35
0.5
I
OZH
Off-State Output Current,
V
CC
=
Max, G at 2V,
20
A
HIGH Level Voltage Applied
V
O
=
2.7V
I
OZL
Off-State Output Current,
V
CC
=
Max, G at 2V
-
400
A
LOW Level Voltage Applied
V
O
=
0.4V
I
I
Input Current at
V
CC
=
Max
A or B
V
I
=
5.5V
0.1
mA
Maximum Input Voltage
DIR or G
V
I
=
7V
0.1
I
IH
HIGH Level Input Current
V
CC
=
Max, V
IH
=
2.7
20
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
IL
=
0.4V
-
0.4
mA
I
OS
Short Circuit Output Current (Note 5) V
CC
=
Max
-
40
-
225
mA
I
CC
Total Supply
Outputs HIGH
V
CC
=
Max,
48
70
Current
Outputs LOW
Outputs Open
62
90
mA
Outputs at Hi-Z
64
95
3
www.fairchildsemi.com
DM74LS645
Switching Characteristics
at V
CC
=
5V and T
A
=
25
C
From (Input)
R
L
=
667
Symbol
Parameter
To (Output)
C
L
=
45 pF
C
L
=
5 pF
Units
Min
Max
Min
Max
t
PLH
Propagation Delay Time
A to B
15
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
A to B
15
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
B to A
15
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
B to A
15
ns
HIGH-to-LOW Level Output
t
PZL
Output Enable Time
G to A
40
ns
to LOW Level
t
PZH
Output Enable Time
G to A
40
ns
to HIGH Level
t
PZL
Output Enable Time
G to B
40
ns
to LOW Level
t
PZH
Output Enable Time
G to B
40
ns
to HIGH Level
t
PLZ
Output Disable Time
G to A
25
ns
to LOW Level
t
PHZ
Output Disable Time
G to A
25
ns
to HIGH Level
t
PLZ
Output Disable Time
G to B
25
ns
to LOW Level
t
PHZ
Output Disable Time
G to B
25
ns
to HIGH Level
www.fairchildsemi.com
4
DM74LS645
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
www.fairchildsemi.com
DM74LS645
Octa
l
Bus T
r
anscei
ver
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
PDF 
ZIP