2000 Fairchild Semiconductor Corporation
DS006436
www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS670
3-
ST
A
T
E 4-by-
4 R
e
gist
er Fil
e
DM74LS670
3-STATE 4-by-4 Register File
General Description
These register files are organized as 4 words of 4 bits
each, and separate on-chip decoding is provided for
addressing the four word locations to either write-in or
retrieve data. This permits writing into one location, and
reading from another word location, simultaneously.
Four data inputs are available to supply the word to be
stored. Location of the word is determined by the write
select inputs A and B, in conjunction with a write-enable
signal. Data applied at the inputs should be in its true form.
That is, if a high level signal is desired from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data
will be accepted only if both internal address gate inputs
are HIGH. When this condition exists, data at the D input is
transferred to the latch output. When the write-enable
input, G
W
, is HIGH, the data inputs are inhibited and their
levels can cause no change in the information stored in the
internal latches. When the read-enable input, G
R
, is HIGH,
the data outputs are inhibited and go into the high imped-
ance state.
The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual
decoding gates are used to complete the address for read-
ing a word. When the read address is made in conjunction
with the read-enable signal, the word appears at the four
outputs.
This arrangement--data entry addressing separate from
data read addressing and individual sense line -- elimi-
nates recovery times, permits simultaneous reading and
writing, and is limited in speed only by the write time (27 ns
typical) and the read time (24 ns typical). The register file
has a non-volatile readout in that data is not lost when
addressed.
All inputs (except read enable and write enable) are buff-
ered to lower the drive requirements to one normal Series
DM74LS load, and input clamping diodes minimize switch-
ing transients to simplify system design. High speed, dou-
ble ended AND-OR-INVERT gates are employed for the
read-address function and have high sink current, 3-STATE
outputs. Up to 128 of these outputs may be wire-AND con-
nected for increasing the capacity up to 512 words. Any
number of these registers may be paralleled to provide n-
bit word length.
Features
s
For use as:
Scratch pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
s
Separate read/write addressing permits simultaneous
reading and writing
s
Organized as 4 words of 4 bits
s
Expandable to 512 words of n-bits
s
3-STATE versions of DM74LS170
s
Fast access times 20 ns typ
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package Number
Package Description
DM74LS670M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS670N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
3
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DM74LS670
Absolute Maximum Ratings
(Note 4)
Note 4: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 5: T
A
=
25
C and V
CC
=
5V.
Note 6: Times are with respect to the Write-Enable input. Write-Select time will protect the data written into the previous address. If protection of data in the
previous address, t
SETUP
(W
A
, W
B
) can be ignored. As any address selection sustained for the final 30 ns of the Write-Enable pulse and during t
H
(W
A
, W
B
)
will result in data being written into that location. Depending on the duration of the input conditions, one or a number of previous addresses may have been
written into.
Note 7: Latch time is the time allowed for the internal output of the latch to assume the state of new data. This is important only when attempting to read from
a location immediately after that location has received new data.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
2.6
mA
I
OL
LOW Level Output Current
24
mA
t
W
Write Enable Pulse Width (Note 5)
25
ns
t
SU
Setup Time
Data
10
ns
(Note 5)(Note 6)
W
A
, W
B
15
t
H
Hold Time
Data
15
ns
(Note 5)(Note 6)
W
A
, W
B
5
t
LATCH
Latch Time for New Data (Note 5)(Note 7)
25
ns
T
A
Free Air Operating Temperature
0
70
C
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4
DM74LS670
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 8: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 10: I
CC
is measured with 4.5V applied to all DATA inputs and both ENABLE inputs, all ADDRESS inputs are grounded and all outputs are OPEN.
Switching Characteristics
at V
CC
=
5V and T
A
=
25
C
Note 11: C
L
=
5 pF.
Symbol
Parameter
Conditions Min
Typ
Max
Units
(Note 8)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.5
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.4
3.4
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW
Level V
CC
=
Min, I
OL
=
Max
0.34
0.5
V
Output Voltage
I
OL
=
Max, V
IH
=
Min
I
I
Input Current @ Max
V
CC
=
Max
D, R or W
0.1
Input Voltage
V
I
=
7V
G
W
0.2
mA
G
R
0.3
I
IH
HIGH Level
V
CC
=
Max
D, R or W
20
Input Current
V
I
=
2.7V
G
W
40
A
G
R
60
I
IL
LOW
Level V
CC
=
Max
D, R or W
-
0.4
Input Current
V
I
=
0.4V
G
W
-
0.8
mA
G
R
-
1.2
I
OZH
Off-State Output Current with
V
CC
=
Max, V
O
=
2.7V
20
A
HIGH Level Output Voltage Applied V
IH
=
Min, V
IL
=
Max
I
OZL
Off-State Output Current with
V
CC
=
Max, V
O
=
0.4V
-
20
A
LOW Level Output Voltage Applied V
IH
=
Min, V
IL
=
Max
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 9)
-
20
-
100
mA
I
CC
Supply Current
V
CC
=
Max (Note 10)
30
50
mA
R
L
=
667
Symbol
Parameter
From (Input)
C
L
=
45 pF
C
L
=
150 pF
Units
To (Output)
Min
Max
Min
Max
t
PLH
Propagation Delay Time
Read Select to Q
40
50
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Read Select to Q
45
55
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Write Enable to Q
45
55
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Write Enable to Q
50
60
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Data to Q
45
55
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Data to Q
40
50
ns
HIGH-to-LOW Level Output
t
PZH
Output Enable Time
Read Enable to Any Q
35
45
ns
to HIGH Level Output
t
PZL
Output Enable Time
Read Enable to Any Q
40
50
ns
to LOW Level Output
t
PHZ
Output Disable Time from
Read Enable to Any Q
50
ns
HIGH Level Output (Note 11)
t
PLZ
Output Disable Time from
Read Enable to Any Q
35
ns
LOW Level Output (Note 11)
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