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Электронный компонент: DM74LS83A

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2000 Fairchild Semiconductor Corporation
DS006378
www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS83A 4-Bi
t Bina
ry Adder w
i
th

Fast

Car
r
y
DM74LS83A
4-Bit Binary Adder with Fast Carry
General Description
These full adders perform the addition of two 4-bit binary
numbers. The sum (
) outputs are provided for each bit
and the resultant carry (C4) is obtained from the fourth bit.
These adders feature full internal look ahead across all four
bits. This provides the system designer with partial look-
ahead performance at the economy and reduced package
count of a ripple-carry implementation.
The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be
accomplished without the need for logic or level inversion.
Features
s
Full-carry look-ahead across the four bits
s
Systems achieve partial look-ahead performance with
the economy of ripple carry
s
Typical add times
Two 8-bit words 25 ns
Two 16-bit words 45 ns
s
Typical power dissipation per 4-bit adder 95 mW
Ordering Code:
Connection Diagram
Order Number
Package Number
Package Description
DM74LS83AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com
2
DM
74L
S
8
3A
Truth Table
H
=
HIGH Level, L
=
LOW Level
Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs
1 and
2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and
B4 are then used to determine outputs
3,
4, and C4.
Logic Diagram
3
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DM74LS83A
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 2: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: I
CC1
is measured with all outputs open, all B inputs LOW and all other inputs at 4.5V, or all inputs at 4.5V.
Note 5: I
CC2
is measured with all outputs OPEN and all inputs grounded.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
0.4
mA
I
OL
LOW Level Output Current
8
mA
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 2)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.5
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.7
3.4
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW
Level V
CC
=
Min, I
OL
=
Max
0.35
0.5
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
I
OL
=
4 mA, V
CC
=
Min
0.25
0.4
I
I
Input Current @ Max
V
CC
=
Max
A or B
0.2
mA
Input Voltage
V
I
=
7V
C0
0.1
I
IH
HIGH Level
V
CC
=
Max
A or B
40
A
Input Current
V
I
=
2.7V
C0
20
I
IL
LOW
Level V
CC
=
Max
A or B
-
0.8
mA
Input Current
V
I
=
0.4V
C0
-
0.4
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 3)
-
20
-
100
mA
I
CC1
Supply Current
V
CC
=
Max (Note 4)
19
34
mA
I
CC2
Supply Current
V
CC
=
Max (Note 5)
22
39
mA
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4
DM
74L
S
8
3A
Switching Characteristics
at V
CC
=
5V and T
A
=
25
C
From (Input)
R
L
=
2 k
Symbol
Parameter
To (Output)
C
L
=
15 pF
C
L
=
50 pF
Units
Min
Max
Min
Max
t
PLH
Propagation Delay Time
C0 to
1 or
2
24
28
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
C0 to
1 or
2
24
30
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
C0 to
3
24
28
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
C0 to
3
24
30
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
C0 to
4
24
28
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
C0 to
4
24
30
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
A
i
, B
i
to
i
24
28
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
A
i
, B
i
to
i
24
30
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
C0 to C4
17
24
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
C0 to C4
17
25
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
A
i
, B
i
to C4
17
24
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
A
i
, B
i
to C4
17
26
ns
HIGH-to-LOW Level Output
5
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DM74LS83A 4-Bi
t Bina
ry Adder w
i
th

Fast

Car
r
y
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
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which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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