2000 Fairchild Semiconductor Corporation
DS006459
www.fairchildsemi.com
August 1986
Revised April 2000
DM74S1
1
2
Dual
Negat
i
ve
-Edge-
T
ri
ggered
Mast
er-
S
l
ave J-K Fli
p
-
F
lop wit
h
Pr
eset,
C
l
ear
, and
Compl
e
m
e
nt
ary
Out
puts
DM74S112
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. Data on the J and
K inputs can be changed while the clock is HIGH or LOW
without affecting the outputs as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Connection Diagram
Function Table
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
L
=
LOW Logic Level
=
Negative going edge of pulse.
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
*
=
This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Toggle
=
Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
Order Number
Package Number
Package Description
DM74S112
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H*
H*
H
H
L
L
Q
0
Q
0
H
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
Toggle
H
H
H
X
X
Q
0
Q
0
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2
DM74S1
1
2
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: C
L
=
15 pF, R
L
=
280
, T
A
=
25
C and V
CC
=
5V.
Note 3: C
L
=
50 pF, R
L
=
280
, T
A
=
25
C and V
CC
=
5V.
Note 4: T
A
=
25
C and V
CC
=
5V.
Note 5: The symbol (
) indicates the falling edge at the clock pulse is used for reference.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
1
mA
I
OL
LOW Level Output Current
20
mA
f
CLK
Clock Frequency (Note 2)
0
125
80
MHz
f
CLK
Clock Frequency (Note 3)
0
80
60
MHz
t
W
Pulse Width
Clock HIGH
6
(Note 2)
Clock LOW
6.5
ns
Clear LOW
8
Preset LOW
8
t
W
Pulse Width
Clock HIGH
8
(Note 3)
Clock LOW
8
ns
Clear LOW
10
Preset LOW
10
t
SU
Setup Time (Note 4)(Note 5)
7
ns
t
H
Input Hold Time (Note 4)(Note 5)
0
ns
T
A
Free Air Operating Temperature
0
70
C
3
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DM74S1
1
2
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Note 6: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 7: Clear is tested with preset HIGH and preset is tested with clear HIGH.
Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 9: With all outputs OPEN, I
CC
is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock input is grounded.
Switching Characteristics
at V
CC
=
5V and T
A
=
25
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.7
3.4
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW Level
V
CC
=
Min, I
OL
=
Max
0.5
V
Output Voltage
V
IH
=
Min, V
IL
=
Max
I
I
Input Current @ Max Input Voltage V
CC
=
Max, V
I
=
5.5V
1
mA
I
IH
HIGH Level
V
CC
=
Max
J, K
50
Input Current
V
I
=
2.7V
Clear
100
A
Preset
100
Clock
100
I
IL
LOW Level
V
CC
=
Max
J, K
-
1.6
Input Current
V
I
=
0.5V
Clear
-
7
mA
(Note 7)
Preset
-
7
Clock
-
4
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 8)
-
40
-
100
mA
I
CC
Supply Current
V
CC
=
Max (Note 9)
30
50
mA
R
L
=
280
Symbol
Parameter
From (Input)
C
L
=
15 pF
C
L
=
50 pF
Units
To (Output)
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
80
60
MHz
t
PLH
Propagation Delay Time
Preset to Q
7
9
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Preset to Q
7
12
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Clear to Q
7
9
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clear to Q
7
12
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Clock to Q or Q
7
9
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock to Q or Q
7
12
ns
HIGH-to-LOW Level Output
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4
DM74S1
1
2
Dual
Negat
iv
e-Edge-
T
r
i
ggere
d
Mast
er-
S
l
ave J-K Fl
ip-
F
lop wit
h
Pr
eset,
C
l
ear
, and
Compl
e
m
ent
ary
O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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