2000 Fairchild Semiconductor Corporation
DS006472
www.fairchildsemi.com
August 1986
Revised April 2000
DM74S174 D
M
74S175
Hex/
Quad
D Fli
p
-Fl
op w
i
t
h
Cl
ear
DM74S174 DM74S175
Hex/Quad D Flip-Flop with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (DM74S175) versions feature comple-
mentary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
s
DM74S174 contain six flip-flops with single-rail outputs.
s
DM74S175 contain four flip-flops with double-rail out-
puts.
s
Buffered clock and direct clear inputs
s
Individual data input to each flip-flop
s
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
s
Typical clock frequency 110 MHz
s
Typical power dissipation per flip-flop 75mW
Ordering Code:
Connection Diagrams
DM74S174
DM74S175
Order Number
Package Number
Package Description
DM74S174N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74S175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
DM74S174
D
M
74S175
Function Table
(Each Flip-Flop)
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Don't Care
=
Transition from LOW-to-HIGH level
Q
0
=
The level of Q before the indicated steady-state input conditions were established.
Note 1: DM74S175 only.
Logic Diagrams
DM74S174
DM74S175
Inputs
Outputs
Clear
Clock
D
Q
Q (Note 1)
L
X
X
L
H
H
H
H
L
H
L
L
H
H
L
X
Q
0
Q
0
3
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DM74S174
D
M
74S175
Absolute Maximum Ratings
(Note 2)
Note 2: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 3: C
L
=
15 pF, R
L
=
280
, T
A
=
25
C and V
CC
=
5V.
Note 4: C
L
=
50 pF, R
L
=
280
, T
A
=
25
C and V
CC
=
5V.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
1
mA
I
OL
LOW Level Output Current
20
mA
f
CLK
Clock Frequency (Note 3)
0
110
75
MHz
f
CLK
Clock Frequency (Note 4)
0
90
65
MHz
t
W
Pulse Width
Clock
7
ns
(Note 3)
Clear
10
Pulse Width
Clock
9
(Note 4)
Clear
12
t
SU
Data Setup Time (Note 3)
5
ns
Data Setup Time (Note 4)
7
t
H
Data Hold Time (Note 3)
3
ns
Data Hold Time (Note 4)
5
t
REL
Clear Release Time (Note 3)
5
ns
Clear Release Time (Note 4)
7
T
A
Free Air Operating Temperature
0
70
C
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4
DM74S174
D
M
74S175
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Note 5: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7: With all outputs OPEN and 4.5V applied to all DATA and CLEAR inputs, I
CC
is measured after a momentary ground, then 4.5V applied to the CLOCK
input.
Switching Characteristics
at V
CC
=
5V and T
A
=
25
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 5)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.7
3.4
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW Level
V
CC
=
Min, I
OL
=
Max
0.5
V
Output Voltage
V
IH
=
Min, V
IL
=
Max
I
I
Input Current @ Max Input Voltage
V
CC
=
Max, V
I
=
5.5V
1
mA
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
50
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.5V
-
2
mA
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 6)
-
40
-
100
mA
I
CC
Supply Current (DM74S174)
V
CC
=
Max (Note 7)
90
144
mA
I
CC
Supply Current (DM74S175)
V
CC
=
Max (Note 7)
60
96
mA
R
L
=
280
Symbol
Parameter
From (Input)
C
L
=
15 pF
C
L
=
50 pF
Units
To (Output)
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
75
65
MHz
t
PLH
Propagation Delay Time
Clock to Output
12
15
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock to Output
17
21
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Clear to Q
15
18
ns
LOW-to-HIGH Level Output (DM74S175 Only)
t
PHL
Propagation Delay Time
Clear to Q
22
23
ns
HIGH-to-LOW Level Output
5
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DM74S174
D
M
74S175
Hex/
Quad
D Fli
p
-Fl
op w
i
t
h
Cl
ear
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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