2000 Fairchild Semiconductor Corporation
DS006486
www.fairchildsemi.com
August 1986
Revised May 2000
DM74S373
D
M
74S374
3-
ST
A
T
E
O
c
tal
D-
T
y
pe T
r
anspar
ent
Latc
hes and
Edge-
T
ri
ggered
Fl
ip-
F
lop
s
DM74S373 DM74S374
3-STATE Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM74S373 are transparent D-type
latches meaning that while the enable (G) is HIGH the Q
outputs will follow the data (D) inputs. When the enable is
taken LOW the output will be latched at the level of the
data that was set up.
The eight flip-flops of the DM74S374 are edge-triggered D-
type flip-flops. On the positive transition of the clock, the Q
outputs will be set to the logic states that were set up at the
D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines
simplify system design as ac and dc noise rejection is
improved by typically 400 mV due to the input hysteresis. A
buffered output control input can be used to place the eight
outputs in either a normal logic state (HIGH or LOW logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines signifi-
cantly.
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be
retained or new data can be entered even while the outputs
are OFF.
Features
s
Choice of 8 latches or 8 D-type flip-flops in a single
package
s
3-STATE bus-driving outputs
s
Full parallel-access for loading
s
Buffered control inputs
s
P-N-P input reduce D-C loading on data lines
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
DM74S373N
DM74S374N
Order Number
Package Number
Package Description
DM74S373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74S373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74S374WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74S374N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
DM74S373
D
M
74S374
Truth Tables
DM74S373
H
=
HIGH Level (Steady State)
L
=
LOW Level (Steady State)
X
=
Don't Care
Z
=
High Impedance State
=
Transition from LOW-to-HIGH level,
Q
0
=
The level of the output before steady-state input conditions were
established.
DM74S374
Logic Diagrams
74S373
Transparent Latches
74S374
Positive-Edge-Triggered Flip-Flops
Output
Enable
D
Output
Control
G
L
H
H
H
L
H
L
L
L
L
X
Q
0
H
X
X
Z
Output
Clock
D
Output
Control
L
H
H
L
L
L
L
L
X
Q
0
H
X
X
Z
3
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DM74S373
D
M
74S374
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
DM74S373 Recommended Operating Conditions
Note 2: C
L
=
15 pF, R
L
=
280
, T
A
=
25
C and V
CC
=
5V.
Note 3: C
L
=
50 pF and R
L
=
280
, T
A
=
25
C and V
CC
=
5V.
Note 4: The symbol (
) indicates the falling edge of the clock pulse is used for reference.
Note 5: T
A
=
25
C and V
CC
=
5V.
DM74S373 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Note 6: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
6.5
mA
I
OL
LOW Level Output Current
20
mA
t
W
Pulse Width (Note 2)
Enable HIGH
6
ns
Enable LOW
7.3
t
W
Pulse Width (Note 3)
Enable HIGH
15
ns
Enable LOW
15
ns
t
SU
Data Setup Time (Note 4)(Note 5)
0
ns
t
H
Data Hold Time (Note 4)(Note 5)
10
ns
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.4
3.2
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW Level
V
CC
=
Min, I
OL
=
Max
0.5
V
Output Voltage
V
IH
=
Min, V
IL
=
Max
I
I
Input Current @ Max Input Voltage V
CC
=
Max, V
I
=
5.5V
1
mA
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
50
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.5V
-
250
A
I
OZH
Off-State Output Current with
V
CC
=
Max, V
O
=
2.4V
50
A
HIGH Level Output Voltage Applied V
IH
=
Min, V
IL
=
Max
I
OZL
Off-State Output Current with
V
CC
=
Max, V
O
=
0.5V
-
50
A
LOW Level Output Voltage Applied V
IH
=
Min, V
IL
=
Max
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 7)
-
40
-
100
mA
I
CC
Supply Current
V
CC
=
Max
Outputs HIGH or LOW
105
160
mA
Outputs Disabled
190
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4
DM74S373
D
M
74S374
DM74S373 Switching Characteristics
at V
CC
=
5V and T
A
=
25
C
Note 8: C
L
=
5 pF
DM74S374 Recommended Operating Conditions
Note 9: C
L
=
15 pF, R
L
=
280
, T
A
=
25
C and V
CC
=
5V.
Note 10: C
L
=
50 pF, R
L
=
280
, T
A
=
25
C and V
CC
=
5V.
Note 11: The symbol (
) indicates the rising edge of the clock pulse is used for reference.
Note 12: T
A
=
25
C and V
CC
=
5V.
R
L
=
280
Symbol
Parameter
From (Input)
C
L
=
15 pF
C
L
=
50 pF
Units
To (Output)
Min
Max
Min
Max
t
PLH
Propagation Delay Time
Data to Any Q
12
14
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Data to Any Q
12
16
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Enable to Any Q
14
14
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Enable to Any Q
18
21
ns
HIGH-to-LOW Level Output
t
PZH
Enable Time to
Output Control to Any Q
15
17
ns
HIGH Level Output
t
PZL
Output Enable Time to
Output Control to Any Q
18
23
ns
LOW Level Output
t
PHZ
Output Disable Time to
Output Control to Any Q
9
ns
HIGH Level Output (Note 8)
t
PLZ
Output Disable Time to
Output Control to Any Q
12
ns
LOW Level Output (Note 8)
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
6.5
mA
I
OL
LOW Level Output Current
20
mA
f
CLK
Clock Frequency (Note 9)
0
75
MHz
f
CLK
Clock Frequency (Note 10)
0
75
MHz
t
W
Pulse Width
Clock HIGH
6
(Note 9)
Clock LOW
7.3
ns
Pulse Width
Clock HIGH
15
(Note 10)
Clock LOW
15
t
SU
Data Setup Time (Note 11)(Note 12)
5
ns
t
H
Data Hold Time (Note 11)(Note 12)
2
ns
T
A
Free Air Operating Temperature
0
70
C
5
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DM74S373
D
M
74S374
DM74S374 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Note 13: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 14: Not more than one output should be shorted at a time, and the duration should not exceed one second.
DM74S374 Switching Characteristics
at V
CC
=
5V and T
A
=
25
C
Note 15: C
L
=
5 pF
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 13)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.4
3.2
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW Level
V
CC
=
Min, I
OL
=
Max
0.5
V
Output Voltage
V
IH
=
Min, V
IL
=
Max
I
I
Input Current @ Max Input Voltage
V
CC
=
Max, V
I
=
5.5V
1
mA
I
H
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
50
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.5V
-
250
A
I
OZH
Off-State Output Current with
V
CC
=
Max, V
O
=
2.4V
50
A
HIGH Level Output Voltage Applied
V
IH
=
Min, V
IL
=
Max
I
OZL
Off-State Output Current with
V
CC
=
Max, V
O
=
0.5V
-
50
A
LOW Level Output Voltage Applied
V
IH
=
Min, V
IL
=
Max
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 14)
-
40
-
100
mA
I
CC
Supply Current
V
CC
=
Max
Outputs HIGH
110
mA
Outputs LOW
90
140
Outputs Disabled
160
R
L
=
280
Symbol
Parameter
From (Input)
C
L
=
15 pF
C
L
=
50 pF
Units
To (Output)
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
75
75
MHz
t
PLH
Propagation Delay Time
Clock to Any Q
15
15
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock to Any Q
17
20
ns
HIGH-to-LOW Level Output
t
PZH
Output Enable Time to
Output Control to Any Q
15
17
ns
HIGH Level Output
t
PZL
Output Enable Time to
Output Control to Any Q
18
23
ns
LOW Level Output
t
PHZ
Output Disable Time from
Output Control to Any Q
9
ns
HIGH Level Output (Note 15)
t
PLZ
Output Disable Time from
Output Control to Any Q
12
ns
LOW Level Output (Note 15)
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6
DM74S373
D
M
74S374
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
7
www.fairchildsemi.com
DM74S373
D
M
74S374
3-
ST
A
T
E
O
c
tal
D-
T
y
pe T
r
anspar
ent
Latc
hes and
Edge-
T
ri
ggered
Fl
ip-
F
lop
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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