www.fairchildsemi.com
REV. 1.0.5 7/22/04
Features
Drives N-channel High-Side and Low-Side MOSFETs in
a synchronous buck configuration
12V High-Side and 12V Low-Side Drive
Internal Adaptive "Shoot-Through" Protection
Integrated Bootstrap Diode for High-Side Drive
Fast rise and fall times
Switching Frequency Up to 500kHz
OD input for Output Disable allows for synchronization
with PWM controller
SOIC-8 Package
Available in low thermal resistance MLP package
Applications
Multi-phase VRM/VRD regulators for Microprocessor
Power
High Current/High Frequency DC/DC Converters
High Power Modular Supplies
General Description
The FAN5009 is a dual, high frequency MOSFET driver,
specifically designed to drive N-Channel power MOSFETs
in a synchronous-rectified buck converter. These drivers,
combined with a Fairchild Multi-Phase PWM controller and
power MOSFETs, form a complete core voltage regulator
solution for advanced microprocessors.
The FAN5009 drives the upper and lower MOSFET gates of
a synchronous buck regulator to 12V
GS
. The upper gate
drive includes an integrated boot diode and requires only an
external bootstrap capacitor (C
BOOT
). The output drivers in
the FAN5009 have the capacity to efficiently switch power
MOSFETs at frequencies up to 500kHz. The circuit's
adaptive shoot-through protection prevents the MOSFETs
from conducting simultaneously.
The FAN5009 is rated for operation from 0C to +85C and
is available in low-cost SOIC-8 or MLP packages.
Typical Application
Figure 1. Typical Application.
SW
FAN5009
12V
VCC
OVERLAP
PROTECTION
CIRCUIT
6
5
7
8
1
PWM
2
C
BOOT
BOOT
VCC
4
Q1
Q2
C
VCC
C
OUT
L1
V
OUT
3
HDRV
LDRV
PGND
OD
FAN5009
Dual Bootstrapped 12V MOSFET Driver
2
REV. 1.0.5 7/22/04
FAN5009
PRODUCT SPECIFICATION
Pin Configuration
Pin Definitions
Functional Block Diagram
Pin #
Pin Name
Pin Function Description
1
BOOT
Bootstrap Supply Input.
Provides voltage supply to high-side MOSFET driver. Connect to
bootstrap capacitor. See Applications Section.
2
PWM
PWM Signal Input.
This pin accepts a logic-level PWM signal from the controller.
3
OD
Output Disable.
When low, this pin disables FET switching (HDRV and LDRV are held low).
4
VCC
Power Input
. +12V chip bias power. Bypass with a 1F ceramic capacitor.
5
LDRV
Low Side Gate Drive Output.
Connect to the gate of low-side power MOSFET(s).
6
PGND
Power ground.
Connect directly to source of low-side MOSFET(s).
7
SW
Switch Node Input
. Connect as shown in Figure 1. SW provides return for high-side
bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection.
8
HDRV
High Side Gate Drive Output
Connect to the gate of high-side power MOSFET(s).
BOOT
PWM
OD
VCC
FAN5009
1
2
3
4
8
7
6
5
HDRV
SW
PGND
LDRV
FAN5009M 8-pin SO-8 package
BOOT
PWM
OD
VCC
FAN5009
1
2
3
4
8
7
6
5
HDRV
Paddle
(Ground)
SW
PGND
LDRV
FAN5009MP 8-pin MLP package
(Paddle should be connected to ground or left floating)
PWM
2
OD
3
2.2
1.2
1
BOOT
VCC
4
SW
7
+
VCC
6
5
LDRV
PGND
8
HDRV
1.2
PRODUCT SPECIFICATION
FAN5009
REV. 1.0.5 7/22/04
3
Absolute Maximum Ratings
Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or other conditions beyond those indicated in
the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for
extended periods may affect device reliability. Absolute maximum ratings apply individually, not in combination.
Unless otherwise specified, voltages are referenced to PGND.
Notes:
1. For transient derating beyond the levels indicated, refer to the graphs on page 7.
Thermal Information
Recommended Operating Conditions
Parameter
Min.
Max.
Units
VCC to PGND
0.3
15
V
PWM and OD pins
0.3
5.5
V
SW to PGND
Continuous
1
15
V
Transient ( t=100nsec, F
500kHz)
5
(1)
25
V
BOOT to SW
0.3
15
V
BOOT to PGND
Continuous
0.3
30
V
Transient ( t=100nsec, F
500kHz)
33
(1)
V
HDRV
V
SW
1
V
BOOT
+0.3
V
LDRV
Continuous
0.5
V
CC
+0.3
V
Transient ( t=200nsec)
2
(1)
V
Parameter
Min.
Typ.
Max.
Units
Junction Temperature (T
J
)
0
150
C
Storage Temperature
65
150
C
Lead Soldering Temperature, 10 seconds
300
C
Vapor Phase, 60 seconds
215
C
Infrared, 15 seconds
220
C
Power Dissipation (P
D
) T
A
= 25C
715
mW
Thermal Resistance, SO8 Junction to Case
JC
40
C/W
Thermal Resistance, SO8 Junction to Ambient
JA
140
C/W
Thermal Resistance, MLP Junction to Paddle
JC
4
C/W
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply Voltage VCC
VCC to PGND
10
12
13.5
V
Ambient Temperature (T
A
)
0
85
C
Junction Temperature (T
J
)
0
125
C
4
REV. 1.0.5 7/22/04
FAN5009
PRODUCT SPECIFICATION
Electrical Specifications
V
CC
= 12V, and T
A
= 25C using circuit in Figure 2 unless otherwise noted. The denotes specifications which apply
over the full operating temperature range.
Figure 2. Test Circuit
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Supply
VCC Voltage Range
V
CC
6.4
12
13.5
V
VCC Current
I
CC
OD = 0V
3.5
8
mA
Bootstrap Diode
Continuous Forward Current
I
F(AVG)
25
mA
Reverse Breakdown Voltage
V
R
15
V
Reverse Recovery Time
2
t
RR
10
ns
Forward Voltage
2
V
F
I
F
= 10mA
0.8
0.95
V
OD Input
Input High Voltage
V
IH (OD)
2.5
V
Input Low Voltage
V
IL (OD)
0.8
V
Input Current
I
OD
OD = 3.0V
300
+300
nA
Propagation Delay
2
t
pdl(OD)
See Figure 3
30
40
ns
t
pdh(OD)
30
45
ns
PWM
Input
Input High Voltage
V
IH(PWM)
3.5
V
Input Low Voltage
V
IL(PWM)
0.8
V
Input Current
I
IL(PWM)
-1
+1
A
High-Side Driver
Output Resistance, Sourcing
Current
R
HUP
V
BOOT
V
SW
= 12V
3.8
4.4
Output Resistance, Sinking
Current
R
HDN
V
BOOT
V
SW
= 12V
1.4
1.8
Transition Times
2,4
t
R(HDRV)
See Figure 2
40
55
ns
t
F(HDRV)
20
30
ns
Propagation Delay
2,3
t
pdh(HDRV)
See Figure 2, and 4
50
65
ns
t
pdl(HDRV)
25
40
ns
FAN5009
1
2
3
4
8
7
6
5
HDRV
SW
PGND
LDRV
BOOT
PWM
OD
VCC
12V
33K
10K
3000pf
3000pf
1
f
PRODUCT SPECIFICATION
FAN5009
REV. 1.0.5 7/22/04
5
Electrical Specifications
(continued)
NOTES:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. AC Specifications guaranteed by design/characterization (not production tested).
3. For propagation delays, "tpdh" refers to low-to-high signal transition and "tpdl" refers to high-to-low signal transition
4. Transition times are defined for 10% and 90% of DC values
Figure 3. Output Disable Timing
Figure 4. Adaptive Gate Drive Timing
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Low-Side Driver
Output Resistance, Sourcing
Current
R
LUP
3.4
4.0
Output Resistance, Sinking
Current
R
LDN
1.4
1.8
Transition Times
2,4
t
R(LDRV)
See Figure 2
40
50
ns
t
F(LDRV)
20
30
ns
Propagation Delay
2,3
t
pdh(LDRV)
See Figures 2, 4
20
30
ns
t
pdl(LDRV)
25
40
ns
t
pdh(ODRV)
See Adaptive Gate
Drive Circuit
description
240
ns
V
IL(OD)
t
pdl(OD)
V
IH(OD)
t
pdh(OD)
LDRV / HDRV
OD
V
IH(PWM)
t
pdl (LDRV)
LDRV
PWM
HDRV-SW
1.2V
V
IL(PWM)
t
pdl (HDRV)
2.2V
t
pdh(LDRV)
SW
t
pdh(HDRV)
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