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REV. 1.0.1 5/2/02

Features

· Implements ACPI control with PWROK, SLP_S3 and

SLP_S5

· Switch and linear regulator controller for 3.3V or 5V Dual
· Linear regulator controller and linear regulator for VADJ

Dual output adjustable from 2.5V to 3.5V

· Break-before-Make
· Drives all N-Channel MOSFETs plus NPN
· Latched overcurrent protection for outputs
· Power-up softstarts for the linear regulators
· UVLO guarantees correct operation for all conditions
· 16 pin SOIC package

Applications

· Willamette Platform ACPI Controller
· Northnwood Platform ACPI Controller

Description

The FAN5067 is an ACPI Switch Controller for Pentium IV
Platforms. It is controlled by PWROK, SLP_S3 and SLP_S5,
and provides 3.3V or 5V Dual and VADJ Dual output for
SDRAM or DDR with 200mA minimum base current for an
external NPN transistor. An on-board precision low TC
reference achieves tight tolerance voltage regulation without
expensive external components. The FAN5067 also offers
integrated Current Limiting that protects each output, and
softstart for the linear regulators. The FAN5067 is available in
a 16 pin SOIC.

Block Diagram

Main

+5V Standby

+3.3V or 5V Dual

+12V

REF

Over Current

+5V Standby

PWR_OK

SLP_S3

Softstart

+5V Main

VADJ Dual

(SDRAM or DDR)

REF

SLP_S5

REF

Osc

-
+

FAN5067

ACPI Dual Switch Controller

FAN5067

PRODUCT SPECIFICATION

REV. 1.0.1 5/2/02

Pin Assignments

Pin Definitions

Pin Number

Pin Name

Pin Function Description

QCAP

Charge pump cap.

Attach flying capacitor between this pin and PUMP to

generate high voltage from standby power.

PUMP

Charge pump switcher.

5VSTBY

5V Standby.

Apply +5V standby on this pin to run the circuit in standby mode.

DUALOUT1

Dual output main gate control.

Attach this pin to a transistor powering 3.3V or

5V dual from the main supply.

DUALOUT2

Dual output standby gate control.

Attach this pin to a transistor powering 3.3V

or 5V dual from the 5V standby supply.

DUALFB

Dual output voltage Feedback.

Pin 6 is used as the input for the voltage

feedback control loop for 3.3V or 5V dual.

SLP_S3

SLP_S3.

Control signal governing the Soft Off state S3. Internal current source

pulls this line high if left open.

SLP_S5

SLP_S5.

Control signal governing the Soft Off state S5. Internal current source

pulls this line high if left open.

PWR_OK

PWR_OK.

Control signal for switches. Internal current source pulls this line high if

left open.

Softstart.

Attach a capacitor to this pin to determine the softstart rate.

GND

Ground.

Connect this pin to ground.

VADJFB

Adjustable Dual Voltage Feedback.

Pin 12 is used as the input for the voltage

feedback loop for the adjustable dual voltage.

VADJ

Adjustable Dual Voltage

. Pin 13 sources VADJ during standby.

VADJOUT

Adjustable Dual Voltage Base Control.

Attach this pin to an NPN transistor

powering VADJ from the 5V Main.

5VMAIN

5V Main.

Apply +5V Main on this pin to run the VADJ base drive.

VCCP

Main Power.

Apply +12V through a diode on this pin to run the circuit in normal

mode. Bypass with a 0.1µF capacitor. When 12V is not present, this pin produces
voltage doubled 5V standby.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

FAN5067

QCAP

PUMP

5VSTBY

DUALOUT1
DUALOUT2

DUALVFB

SLP_S3
SLP_S5

VCCP
5VMAIN
VADJOUT
VADJ
VADJFB
GND
SS
PWR_OK

FAN5067

PRODUCT SPECIFICATION

REV. 1.0.1 5/2/02

Note:

1. Voltage Regulation includes Initial Voltage Setpoint and Output Temperature Drift.

Electrical Specifications

+5VSTBY

= V

+5VMAIN

=5V, V

+3.3V

= 3.3V, V

+12V

= 12V and T

= +25°C using circuit in Figure 4, unless otherwise noted.)

The · denotes specifications which apply over the full operating temperature range.

Parameter

Conditions

Min.

Typ.

Max.

Units

DUAL Output

Out1

, On

Out1

, Off

I = 10µA

200

Out2

, On

Standby

Total Output Voltage Variation

DUALOUT2 On

3.135

3.3

3.465

Maximum Drive Current

DUALOUT1 On

100

Minimum Load Current

DUALOUT2 On

Overcurrent Limit: Undervoltage

%Vout

Overcurrent Delay Time

150

µsec

Output Driver Deadtime

See Figure 2: Main

Standby

µsec

See Figure 2: Standby

Main

200

1000

nsec

VADJ DUAL

> 3.3V

100

3.3V

150

Total Voltage Variation

= R

= 10K

2.375

2.5

2.625

VADJ Output Voltage Range

1.25

3.5

VADJ Current

365

400

Overcurrent Limit

%Vref

Overcurrent Delay Time

150

µsec

Output Driver Overlap Time

See Figure 2

µsec

Common Functions

Charge Pump Frequency

250

KHz

+5VSTBY UVLO

4.5

+5VSTBY UVLO Hysteresis

0.5

+12V UVLO

7.5

+12V UVLO Hysteresis

800

+5VSTBY Current

MAIN Power Present

+12V Current

2.5

Input Logic HIGH

2.0

Input Logic LOW

0.8

Softstart Current

µA

Control Line Input Current

SLP_S5, SLP_S3, PWROK

100

µA

Over Temperature Shutdown

150

°C

FAN5067

PRODUCT SPECIFICATION

REV. 1.0.1 5/2/02

Application Information

The FAN5067 Controller

The FAN5067 is a fully compliant ACPI controller IC. Used
with an ATX power supply, it generates a 3.3V or 5V Dual
and power for either SDRAM or DDR, and has a large array
of additional protection functions integrated in.

Overview of ACPI

The Advanced Configuration and Power Interface, or ACPI,
is a system for controlling the use of power in a computer. It
enables the computer manufacturer and the computer user to
determine the computer's power usage dynamically. For
example, when the computer has been unused for a certain
time, the monitor and peripherals could be turned off, and
their states saved to memory. After a longer period, the pro-
cessor could be turned off, and the memory saved to disk. A
peripheral could then re-awaken the entire system on the
occurrence of an event, such as the arrival of a FAX on a
modem.

As shown in Figure 5, the available power inputs to the com-
puter system from the ATX power supply are +5V main, +12V
main, +3.3V main, and +5V standby. "Main" means that
these power outputs are available under full-power operation
of the system, but can be turned off in some of the power-
saving modes. "Standby" means that this power output is
always present.

The most general ACPI system requires four dual outputs:
5V dual, 3.3V dual, 3.3V SDRAM, and 2.5V dual. "Dual"
means that the power can be (but is not necessarily) present
whether the main power supplies are present or not. To
ensure the presence of these outputs, while not overloading
the standby power, they have dual inputs, from both main
power and standby. The presence or absence of the dual out-
puts is determined by the control signals to the FAN5067.

ACPI States

As shown in Table 1, there are three ACPI states that are of
primary concern to the system designer, designated S0, S3
and S5. S0 is the full-power state, the state of the computer
when it is being actively used. The other two states are sleep
states, reflecting differing levels of power-down.

S3 is a state in which the processor is powered down, but its
last state is being preserved in IC memory, which is kept on.
Since memory is fast, the computer can quickly come back
up to full operation. However, this state continues to draw
moderate power, due to the memory being kept alive.

S5 is a state in which memory is off, and the last state of the
processor has been written to the hard disk. Since the disk is
slow, the computer takes longer to come back to full operation.
However, since memory is off, this state draws minimal
power.

It is anticipated that only the following state transitions will
occur: S0

S3, S0

S5, S3

S5, S5

S0, and S3

S0;

the transition S5

S3 will occur only as an intermediate state

during the transition from S5

S0. To prevent overcurrent

limit from activating, the FAN5067 blocks this transition.
For example, when PWROK = SLP_S3 = 0, and SLP_S5
transitions from 0 to 1, the FAN5067 remains in the S5 state.
See Table 2.

Dual Output

The dual output is intended to power subsystems such as the
computer's PCI slots. A typical application that would
require the use of 3.3V dual rather than +3.3V main for a PCI
slot would be the use of a modem: if the system needs to be
able to awaken from sleep when the modem receives incom-
ing data, then that slot must be powered from dual, because
main power is off. Other slots not requiring dual power can
be configured using the control signals.

3.3V dual can be generated by two MOSFETs, one from
+3.3V main, the other from +5V standby, as shown in Figure
4. When main power is present, the MOSFET Q1 is turned on
as a switch, so that input and output are connected together.
When main power is absent, the MOSFET Q2 is controlled by
the FAN5067 as a linear regulator, generating a regulated 3.3V
from +5V standby. The MOSFET Q1 must be connected as
shown in the figures, to avoid back-feed.

The state of the MOSFETs is controlled by the SLP_S3 and
PWROK lines, as shown in Figure 3. When both SLP_S3 and
PWROK are asserted, the main switch is on, and the linear reg-
ulator is off. If either line is de-asserted, the main switch is
off and the linear regulator is on.

Q1 and Q2 as shown in Table 3 have different R

DS,on

ratings.

In a typical system, it is anticipated that full-power current
will be about 2.4A maximum, and standby current will be
about 500mA maximum. The difference in maximum cur-
rents means that Q2 can be a less expensive device than Q1.

The design of the linear regulator for a 3.3V Dual necessitates
a minimum load current of 50mA. Furthermore, in order to
guarantee stable operation, the output capacitor on the 3.3V
Dual must have a minimum ESR as shown in Figure 6. The
hatched region shows acceptable values of ESR vs. output
capacitance. Values of the output capacitor less than 47µF or
greater than 300µF are not recommended.

5V Dual can be generated by applying 5V main to the source
of Q1, and placing a resistor divider in the feedback to pin 6.

FAN5067

PRODUCT SPECIFICATION

REV. 1.0.1 5/2/02

Figure 6. Recommended C vs. ESR for

Stable Operation of the Dual Output

Adjustable Dual Output

The adjustable dual output is intended to provide power to
SDRAM or DDR memory.

Adjustable dual is generated by one external NPN bipolar
acting as a linear regulator from +5V main, and one linear
regulator internal to the FAN5067 from +5V standby, as
shown in Figure 4, and in the block diagram on the front
page. When main power is present, the NPN Q3 linear regu-
lates, and when main power is absent, the internal linear reg-
ulator is on. Q3 cannot be substituted with a MOSFET. If
used in one direction, the MOSFET's body diode would per-
mit back-feed; if used in the other direction, it would short-
circuit the linear regulator action.

The state of the external MOSFET and the internal linear
regulator is controlled by the SLP_S3 and PWROK lines,
and additionally the SLP_S5 line, as shown in Figure 3.
When SLP_S5 is de-asserted, both the external MOSFET
and the internal linear regulator are off, and there is no out-
put voltage on the 3.3V SDRAM line.

If the SLP_S5 line is asserted, the adjustable dual output is
on. In this condition, if either the SLP_S3 or the PWROK
line, or both, are de-asserted, the linear regulator is on and
the MOSFET is off. Only in the case if both the SLP_S3 and
the PWROK lines are asserted, the MOSFET is on and the
linear regulator is off.

In a typical system, it is anticipated that standby current will
be a maximum of 365mA, and full-power current may be as
high as 2A. This places some significant constraints on the
selection of Q3. Since its input may be as low as (5V 5%)
= 4.75V, there is only 4.75V 3.3V = 1.45mV of V

head-

room for its operation as a linear regulator. For this reason
the FAN5067 can provide up to 200mA of steady-state base
current. The TIP41A device shown has a sufficiently low
V

CE, sat

to guarantee worst-case regulation even at 2A I

with

this base current.

The output voltage of the Adjustable Dual is set with two
resistors as shown in Figure 4, according to the equation.

Dynamic Change of Adjust Output

There may be circumstances under which it is desired to
dynamically change the output of the adjustable dual output.
For example, a circuit that switches from 2.5V to 3.3V is
shown in Figure 7.

Figure 7. Circuit for Dynamic Change of Output Voltage

of the Adjustable

A potential problem arises when using this circuit, however:
When the transistor is turned on, the voltage on the VADJFB
pin abruptly drops, until the output of the linear regulator can
charge up the output caps. If the voltage to which it drops is
less than about 80% of 1.25V, or 1.00V, the OC limit will trip
and shut down the IC. This happens in this example because

To avoide this problem, systems that intended to dynami-
cally change the output voltage of the adjustable dual output
should disable the OC protection with the circuit shown in
Figure 8.

Figure 8. Circuit to Disable OC Protection

100

330

100

200

C (

µF)

ESR (m

)

300

400

200

300

Vadj

1.25V

-------------------

3.3V

VADJFB

VADJ

2.5V

(

)

(

) R1

[

]

-----------------------------------------

0.94V

2N3906

500K

1N4148

µF

+5V_SB

PRODUCT SPECIFICATION

FAN5067

REV. 1.0.1 5/2/02

FAN5067 ACPI Control Lines

As already discussed, the FAN5067 outputs are controlled
by the three ACPI control lines, SLP_S3, SLP_S5 and
PWROK, as summarized in Tables 1 and 2. System design-
ers must in particular be careful to ensure that their system is
designed with SLP_S5, not SLP_S5; if SLP_S5 is used, it
must be inverted before being used with the FAN5067.

The control lines have internal pull-ups of approximately
40µA, and so can be controlled by open collector drivers if
desired. In a noisy system, it may be desirable to filter these
lines, which can be done with a 1K

resistor and a small

capacitor.

FAN5067 Dynamic Operation

The FAN5067 is designed to minimize the output capaci-
tance required to hold up the various output lines during
transitions between different states. Thus in particular, the
adjustable dual output has guaranteed minimum overlap
time, the time (as shown in Figure 2) during a state transition
during which both main and standby are connected to the
output. This overlap time guarantees that a power source is
always connected to the output, so that there will be no dip in
the output voltage during state transitions. There is also a
maximum overlap time, to ensure that the standby power
doesn't have to source main power very long, thus minimiz-
ing thermal stress on the standby device.

The dual output is different because it is powered by both a
linear regulator and a switch. If the linear regulator were to
turn on while the switch is on (or vice versa) the linear regu-
lator would supply power to the main line through the
switch. For this reason, the linear regulator must be off
before the switch is on, and vice versa. Thus, this output has
guaranteed minimum deadtime when both linear regulator
and switch are off. During this time, the output capacitor
must hold up the load, and so there is also a specified maxi-
mum deadtime, allowing a maximum necessary capacitance
to be selected, see below.

Stability

As with all linear regulators, the FAN5067's linear regulators
require a minimum load. With the exception of the 3.3V dual
output, however, all of these minimum loads are internal to
the FAN5067. The dual output requires a minimum load of
50mA; if a situation may occur in which the load is less than
50mA, additional steps may be necessary to ensure stability.

Furthermore, depending on location, it may be necessary to
bypass the drain (or collector) of the linear regulator with a
low ESR capacitor for stability. As a rule of thumb, if the
pass element is more than 1" from its power source, it should
have a bypass.

Softstart

Pin 10 of the FAN5067 functions as a softstart. When power
is first applied to the chip, a constant current is applied from
the pin into an external capacitor, linearly ramping up the
voltage. This ramp in turn controls the internal reference of
the FAN5067. providing a softstart for the linear regulators.
The actual state of the FAN5067 on power up will be deter-
mined by the state of its control lines.

The switches in the system must be either on or off, and so
softstart has no effect on their characteristics: if the appropri-
ate control signals are asserted, they will turn on at once.

The softstart is effective only during power on. During a
transition between states, such as from S5

S0, the linear

regulators are not softstarted.

It is important to note that the softstart pin is not an enable;
pulling it low will not necessarily turn off all outputs.

Charge Pump

In main power operation, the FAN5067 is run from the +12V
main supply. This supply also provides voltage to the various
MOSFET gates. However, during standby, this supply is off.
To provide power to the chip and the appropriate gates, the
FAN5067 incorporates a free-running charge pump. As
shown in Figure 4, and in the block diagram on the front
page, a capacitor attached between pins 1 and 2 of the
FAN5067 acts as a charge pump with internal diodes. The
charge pump output is internally diode or'red with the 12V
input. The 12V input must have a series diode to prevent
back-feeding the charge pump to the + 12V main when in
standby. The 12V input line needs a bypass capacitor for
high-frequency noise rejection. If desired, the system may be
operated without the 12V or the diode; however, the bypass
capacitor must still be present.

Overcurrent

The FAN5067 does not directly detect current through the
devices that power its outputs. Instead, it monitors the output
voltages. In the event of a hard short, the voltage drops
below 80% of nominal, and all outputs are latched off, and
remain off until 5V standby power is recycled. The overcur-
rent latch off is delayed by 150µsec to prevent nuisance trips.

During softstart, the overcurrent voltage monitors are kept
proportional to the reference, to avoid tripping overcurrent
during startup.

In the S5 state, when the memory outputs are off, the voltage
monitors on the memory lines are disabled, to prevent trip-
ping the overcurrent. When turning these lines back on from
the S5 state, overcurrent is prevented from tripping because
the S3 state is blocked. See Table 2.

If the adjustable dual is not used, its feedback line, pin 12,
must be connected to 5V STBY, to prevent an overcurrent
trip.

FAN5067

PRODUCT SPECIFICATION

REV. 1.0.1 5/2/02

UVLO

If the +5V standby is below approximately 4.5V, the
FAN5067 will leave off or turn off all outputs. Similar com-
ments apply to the +12V main at 7.5V. The +5V standby
UVLO has approximately 0.5V hysteresis, the +12V main
UVLO 1V.

Over Temperature

The FAN5067 is capable of sourcing substantial current,
200mA minimum to the adjustable voltage transistor's base dur-
ing S0 and 144mA to the line during S3. As a result, there can
be heavy power dissipation in the IC. While the FAN5067 is
designed to accept this power dissipation, any overloading of
outputs can cause excessive heating. If the FAN5067 die
temperature exceeds about 150°, all outputs are shut off.
Outputs remain off until the die temperature returns to its
safe area.

Transistor Selection

External transistor selection depends on usage, differing for
the linear regulators and the switches.

The MOSFET switches, should be sized based on regulation
requirements and power dissipation. Since the ATX outputs
are ±5%, the outputs driven from them must be wider. As an
example, if we want to hold 3.3V PCI to -10%, we can drop
only 5% = 165mV across Q1. At 2.4A, this means Ql must
have a maximum R

DS,on

of 165mV/2.7A = 68m

, including

tolerance and self-heating effects. We thus choose a Fairchild
FDC633N, which has 72m

maximum R

DS, on

at 4.5V V

at 25°C. We can estimate power dissipation as (2.4A)

42m

= 270mW, which should be acceptable for this pack-

age.

Q2 is a MOSFET functioning as a linear regulator. Since it
delivers only 500mA, it is easy to select a MOSFET, it need
only be able to handle 500mA * (5V + 5% 3.3V) = 1W.
We select the Fairchild FDS6630A in an SO-8 package.

Q3 is an NPN bipolar functioning as a linear regulator. As
already discussed, it must have a V

CE,sat

lower than 1.45V at

= 2A and I

= 200mA. Its power dissipation can be as

high as (5V + 5%3.3V) * 2A = 3.9W.

Alternate for Adjustable Dual

Instead of the bipolar transistor shown in Figure 4 for Q3, the
linear pass element for the adjustable dual, a MOSFET and
schottky diode can be used as shown in Figure 9.

Figure 9. Adjustable Dual with MOSFET

The schottky should be chosen to have a low V

at the speci-

fied adjustable voltage and current. The MOSFET's R

DS,on

must then be lower than (5V -5% -VADJ -V

)/I

Dual

including

temperature. An additional constraint is that the MOSFET
must have a gate threshold voltage lower than 1.5V. For exam-
ple, for 2.8A @3.3V, choose the diode to be an MBR835, and
the MOSFET a Fairchild FDC653M. This same technique
can then also be used for adjustable currents higher than can
be achieved with the bipolar transistor.

Output Capacitor Selection

Output capacitor selection depends on whether the line has
overlap time or not.

For both the adjustable dual, there is guaranteed overlap time
between when one source is turned on and the other source
turned off. For this output, the output capacitor is not needed
to hold up the supply, but only for noise filtering and to
respond to transient loading.

The dual output has deadtime between when one source is
turned off and the other source turned on. During the time
when both are off, the output current must be supplied by the
output capacitor. Mitigating this, it must be realized that the
system will be designed in such a way that the current has
gone to its sleep value before the transition occurs. For
example, the dual has a sleep current of 500mA maximum.
Maximum deadtime is 6µsec, and so charge depletion is
500mA * 6µsec = 3µC. Suppose that we have a total of
8% drop due to the source tolerance and the MOSFET drop,
and we are trying to hold 10% regulation. The remaining
2% = 66mV implies a minimum capacitance of 3µC/66m
V = 45µF.

FAN5067

5V Main

Adjustable Dual

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