www.fairchildsemi.com
Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor.
REV. 1.0.4 1/29/02
Features
Output programmable in 25mV steps from 1.05V to
1.825V using a dynamically programmable integrated
5-bit DAC
Controls adjustable linears for Vclock (2.5V),
Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), and
Vadj (1.2V nominal)
Remote sense
Programmable Active Droop
TM
up to 200mV
Drives N-Channel MOSFETs
Overcurrent protection using MOSFET sensing
Overvoltage protection including startup
85% efficiency typical at full load
Integrated Power Good and Enable/Soft Start functions
Linears start instantly
Meets Intel VRM8.5 specifications using minimum
number of external components
24 pin SOIC package
Applications
Power supply for Pentium
III Platforms
VRM for Pentium III processor
Programmable multi-output power supply
Description
The FAN5071 is a synchronous mode DC-DC controller IC
which provides a highly accurate, programmable set of output
voltages for multi-voltage platforms such as the Intel Pentium III,
and provides a complete solution for all Intel VRM8.5 CPU
applications, and for other high-performance processors. The
FAN5071 features remote voltage sensing, independently
adjustable current limit, and a proprietary wide-range Pro-
grammable Active Droop
TM
for optimal converter transient
response and VRM8.5 compliance. The FAN5071 uses a 5-bit
D/A converter to dynamically program the output voltage dur-
ing operation from 1.05V to 1.825V in 25mV steps. The
FAN5071 uses a high level of integration to deliver load cur-
rents in excess of 28A from a 5V source with minimal exter-
nal circuitry. Synchronous-mode operation offers optimum
efficiency over the entire specified output voltage range. An
on-board precision low TC reference achieves 0.8% voltage
regulation without expensive external components. The
FAN5071 includes linear regulator controllers for Vclock
(2.5V),Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V),
and Vadjustable (1.2V nominal) each adjustable with an
external divider. The FAN5071 also offers integrated functions
including open-collector Power Good, Output Enable/Soft
Block Diagram
VID3
VID2
VID1
16
VID0
GNDP
23
22
2
18
24
1
17
-
+
-
+
OSC
1.24V
Reference
Digital
Control
Power
Good
5-Bit
DAC
VID4
8 7 6 5 4
+5V
+12V
PWRGD
-
+
ENABLE/SS
VCC
GNDA
3
LODRV
HIDRV
VCCP
21
VCCA
+5V
20
-
REF
REF
PWRGD,
OCL
PWRGD,
OCL
+3.3V
+1.2V/Adj
10
9
+2.5V
12
11
19
OCL
-
+
VCCP
PWRGD, OCL
V
3.3/1.5V
15
14
13
R
D
R
S
-
+
+
-
+
FAN5071
High Performance Programmable Synchronous
DC-DC Controller for Multi-Voltage Platforms
FAN5071
2
REV. 1.0.4 1/29/02
Start and current limiting. The linears start instantly, not
waiting for softstart. The FAN5071 is available in a 24 pin
SOIC package.
Pin Assignments
24
23
22
21
20
19
18
17
16
15
14
13
FAN5071
HIDRV
SW
GNDA
VID4
VID3
VID2
VID1
VID0
VADJGATE
VADJFB
VCKGATE
VCKFB
VCCP
LODRV
GNDP
VCCA
VFB
DROOP
ILIM
PWRGD
SS/ENABLE
TYPEDET
VAGPGATE
VAGPFB
1
2
3
4
5
6
7
8
9
10
11
12
Pin Definitions
Pin Number
Pin Name
Pin Function Description
1
HIDRV
High Side FET Driver.
Connect this pin to the gate of an N-channel MOSFET. The
trace from this pin to the MOSFET gate should be <0.5".
2
SW
High Side Driver Source and Low Side Driver Drain Switching Node.
Together
with DROOP and ILIM pins allows FET sensing for V
CC
current.
3
GNDA
Analog Ground.
Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
4-8
VID4-0
Voltage Identification Code Inputs.
These open collector/TTL compatible inputs
will program the output voltage over the ranges specified in Table 1.
9
VADJGATE
Gate Driver for VADJ Transistor.
For Adjustable output.
10
VADJFB
Voltage Feedback for VADJ.
11
VCKGATE
Gate Driver for VCK Transistor.
For 2.5V output.
12
VCKFB
Voltage Feedback for VCK.
13
VAGPFB
Voltage Feedback for VAGP.
14
VAGPGATE
Gate Driver for VAGP Transistor.
For 3.3/1.5V output.
15
TYPEDET
Type Detect.
Sets 3.3V or 1.5V for AGP.
16
ENABLE/SS
Output Enable.
A logic LOW on this pin will disable all outputs. An internal current
source allows for open collector control. This pin also doubles as soft start for the
switcher.
17
PWRGD
Power Good Flag.
An open collector output that will be logic LOW if any output
voltage is not within 14% of the nominal output voltage setpoint.
18
ILIM
V
CC
Current Feedback.
Pin 18 is used in conjunction with pin 2 as the input for the
V
CC
current feedback control loop. Layout of these traces is critical to system
performance. See Application Information for details.
19
DROOP
Droop Set.
Use this pin to set magnitude of active droop.
20
VFB
Vcc Voltage Feedback.
Pin 20 is used as the input for the V
CC
voltage feedback
control loop. See Application Information for details regarding correct layout.
21
VCCA
Analog V
CC
.
Connect to system 5V supply and decouple with a 0.1F ceramic
capacitor.
22
GNDP
Power Ground.
Return pin for high currents flowing in pin 24 (V
CCP
).
23
LODRV
V
CC
Low Side FET Driver.
Connect this pin to the gate of an N-channel MOSFET
for synchronous operation. The trace from this pin to the MOSFET gate should be
<0.5".
24
VCCP
Power V
CC
.
For all FET drivers. Connect to system 12V supply through a 33
, and
decouple with a 1F ceramic capacitor.
PRODUCT SPECIFICATION
FAN5071
REV. 1.0.4 1/29/02
3
Absolute Maximum Ratings
Note 1:
Component mounted on demo board in free air.
Recommended Operating Conditions
Supply Voltage V
CCP
to GND
15V
Supply Voltage V
CCA
to GND
13.5V
Voltage Identification Code Inputs, VID0-VID4
VCCA
All Other Pins
13.5V
Junction Temperature, T
J
150C
Storage Temperature
-65 to 150C
Lead Soldering Temperature, 10 seconds
300C
Thermal Resistance Junction-to-case,
1
JA
75C/W
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply Voltage V
CCA
4.50
5
5.25
V
Input Logic HIGH
2.0
V
Input Logic LOW
0.8
V
Ambient Operating Temperature
0
70
C
Output Driver Supply, V
CCP
10.8
12
13.2
V
Electrical Specifications
(V
CCA
= 5V, V
CCP
= 12V, V
OUT
= 1.425V, and T
A
= +25C using circuits in Figure 1, unless otherwise noted.)
The denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min.
Typ.
Max. Units
V
CC
Regulator
Output Voltage
See Table I
1.05
1.825
V
Output Current
28
A
Initial Voltage Setpoint
I
LOAD
= 0.8A, V
VID
= 1.425V
1.453
1.465
1.477
V
Output Temperature Drift
T
A
= 0 to 70C, V
VID
= 1.425V
-6
mV
Line Regulation
V
IN
= 4.75V to 5.25V
+10
mV/V
Internal Droop Impedance
3
I
LOAD
= 0.8A to 30A
13.0
14.4
15.8
K
Maximum Programmable Droop
200
mV
Output Ripple
20MHz BW, I
LOAD
= 28A
20
mVpk
Total Output Variation, Steady State
1
V
VID
= 1.425V
3
1.360
1.490
V
Total Output Variation, Transient
2
I
LOAD
= 0.8A to I
max
, V
VID
= 1.425V
1.335
1.515
V
Short Circuit Detect Current
45
50
60
A
Efficiency
I
LOAD
= 18A, V
VID
= 1.425V
83
%
Output Driver Rise & Fall Time
See Figure 3
50
nsec
Output Driver Deadtime
See Figure 3
50
nsec
Duty Cycle
0
100
%
5V UVLO
3.76
4
4.24
V
12V UVLO
7.65
8.5
9.35
V
Soft Start Current
5
10
17
A
FAN5071
4
REV. 1.0.4 1/29/02
Notes:
1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is
measured at the converter's VFB sense point.
2. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than
0.5m
trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal
performance.
3. Using the VFB pin for remote sensing of the converter's output at the load, and the appropriate droop, the converter will be in
compliance with Intel's VRM 8.5 specification. If Intel specifications on maximum plane resistance from the converter's output
capacitors to the CPU are met, the specifications at the capacitors will also be met.
4. PWRGD will be high only if BOTH the linears and the switcher conditions are met. PWRGD will be low if EITHER condition is met.
Adjustable Linear Regulator
Output Voltage
I
LOAD
2A
1.188
1.212
1.236
V
Over Current Trip Level
80
%V
O
VCLK Linear Regulator
Output Voltage
I
LOAD
2A
2.375
2.5
2.625
V
Over Current Trip Level
80
%V
O
VAGP Linear Regulator
Output Voltage
I
LOAD
2A, TYPEDET = 0V
1.425
1.5
1.575
V
Output Voltage
I
LOAD
2A, TYPEDET = OPEN
3.135
3.3
3.465
V
Over Current Trip Level
80
%V
O
Common Functions
Oscillator Frequency
255
300
345
kHz
PWRGD Threshold
4
Switcher
Logic HIGH [V
VID
+ 85mV]
Logic LOW [V
VID
155mV]
88
80
112
120
%
PWRGD Delay Switcher
HIGH
LOW
6
sec
PWRGD Hysteresis Switcher
25
mV
PWRGD Threshold
4
Linear
Regulators
All Outputs
80
%V
out
Electrical Specifications
(Continued)
(V
CCA
= 5V, V
CCP
= 12V, V
OUT
= 1.425V, and T
A
= +25C using circuits in Figure 1, unless otherwise noted.)
The denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min.
Typ.
Max. Units
FAN5071
5
REV. 1.0.4 1/29/02
Table 1. Output Voltage Programming Codes for FAN5071
Note:
1. 0 = processor pin is tied to GND.
1 = processor pin is pulled up to 3.3V.
VID25mV
VID3
VID2
VID1
VID0
Nominal V
OUT
0
0
1
0
0
1.050V
1
0
1
0
0
1.075V
0
0
0
1
1
1.100V
1
0
0
1
1
1.125V
0
0
0
1
0
1.150V
1
0
0
1
0
1.175V
0
0
0
0
1
1.200V
1
0
0
0
1
1.225V
0
0
0
0
0
1.250V
1
0
0
0
0
1.275V
0
1
1
1
1
1.300V
1
1
1
1
1
1.325V
0
1
1
1
0
1.350V
1
1
1
1
0
1.375V
0
1
1
0
1
1.400V
1
1
1
0
1
1.425V
0
1
1
0
0
1.450V
1
1
1
0
0
1.475V
0
1
0
1
1
1.500V
1
1
0
1
1
1.525V
0
1
0
1
0
1.550V
1
1
0
1
0
1.575V
0
1
0
0
1
1.600V
1
1
0
0
1
1.625V
0
1
0
0
0
1.650V
1
1
0
0
0
1.675V
0
0
1
1
1
1.700V
1
0
1
1
1
1.725V
0
0
1
1
0
1.750V
1
0
1
1
0
1.775V
0
0
1
0
1
1.800V
1
0
1
0
1
1.825V
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