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Электронный компонент: FAN5109

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2004 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
October 2005
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
FAN5109
Dual Bootstrapped 12V MOSFET Driver
Features
Drives N-channel High-Side and Low-Side MOSFETs
in a Synchronous Buck Configuration
Enhanced Upgrade to FAN5009
Direct Interface to FAN5019B/FAN5182 and other
compatible PWM Controllers
12V High-Side and 12V Low-Side Drive
Internal Adaptive "Shoot-Through" Protection
Fast Rise and Fall times
Switching Frequency above 500kHz
OD input for Output Disable allows for synchroni-
zation with PWM Controller
SOIC-8 Package
Applications
Multi-phase VRM/VRD Regulators for Microprocessor
Power
High Current/High Frequency DC/DC Converters
High Power Modular Supplies
General Description
The FAN5109 is a high-frequency driver, specifically
designed to drive N-Channel power MOSFETs in a syn-
chronous-rectified buck converter. This driver, combined
with a Fairchild Multi-Phase PWM controller and power
MOSFETs, form a complete core voltage regulator solu-
tion for advanced microprocessors.
The FAN5109 drives the upper and lower MOSFET gates
of a synchronous buck regulator up to 12V
GS
. The
FAN5109's output drivers can efficiently switch power
MOSFETs at frequencies above 500kHz. The circuit's
adaptive shoot-through protection prevents the MOSFETs
from conducting simultaneously.
The FAN5109 is rated for operation from 0C to +85C
and is available in a low-cost SOIC-8 package.
Ordering Information
Note:
Contact Fairchild Sales for availability of leaded parts.
Part Number
Temperature Range
Pb-Free
Package
Packing
Qty/Reel
FAN5109MX
0C to 85C
Yes
SOIC-8
Tape and Reel
2500
2
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Typical Application
Figure 1. Typical Application
Pin Configuration
Figure 2. 8-Pin SOIC Package
Pin Definitions
Pin #
Pin Name
Pin Function Description
1
BOOT
Bootstrap Supply Input.
Provides voltage supply to the high-side MOSFET driver.
Connect to bootstrap capacitor and diode.
2
PWM
PWM Signal Input.
Accepts a logic-level PWM signal from the controller.
3
OD
Output Disable.
When low, this pin disables FET switching (HDRV and LDRV are
held low).
4
VCC
Power Input
. +12V bias power. Bypass with a 1F ceramic capacitor.
5
LDRV
Low Side Gate Drive Output.
Connect to the gate of the low-side power MOSFET(s).
6
PGND
Power Ground.
Connect directly to the source of low-side MOSFET(s) and C
VCC.
7
SW
Switch Node Input
. Connect as shown in Figure 1. SW provides return for the high-side
bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection.
8
HDRV
High Side Gate Drive Output
.
Connect to the gate of the high-side power MOSFET(s).
SW
FAN5109
12V
VCC
OVERLAP
PROTECTION
CIRCUIT
6
5
7
8
1
PWM
2
BOOT
VCC
4
Q1
Q2
L1
3
HDRV
LDRV
PGND
OD
C
BOOT
V
OUT
C
OUT
C
VCC
D1
BOOT
PWM
OD
VCC
FAN5109
1
2
3
4
8
7
6
5
HDRV
SW
PGND
LDRV
3
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FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Functional Block Diagram
Figure 3. Functional Block Diagram
PWM
2
OD
3
V
CC
/3
1.3V
1
BOOT
VCC
4
SW
7
+
V
CC
6
5
LDRV
PGND
8
HDRV
1.3V
V
CC
4
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FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Absolute Maximum Ratings
Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or other conditions beyond those indicated in
the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for
extended periods may affect device reliability. Absolute maximum ratings apply individually, not in combination. Unless
otherwise specified, voltages are referenced to PGND.
Notes:
1.
For transient derating beyond the levels indicated, refer to the graphs on page 9.
Thermal Information
Recommended Operating Conditions
Parameter
Min.
Max.
Unit
VCC to PGND
0.3
15
V
PWM and OD pins
0.3
5.5
V
SW to PGND
Continuous
1
15
V
Transient ( t=100nsec, F
500kHz)
5
(1)
25
V
BOOT to SW
0.3
15
V
BOOT to PGND
Continuous
0.3
30
V
Transient ( t=100nsec, F
500kHz)
38
(1)
V
HDRV V
SW
1
V
BOOT
+0.3
V
LDRV
Continuous
0.5
V
CC
V
Transient ( t=200nsec)
2
(1)
V
CC
+0.3
V
Parameter
Min.
Typ.
Max.
Unit
Junction Temperature (T
J
)
0
150
C
Storage Temperature
65
150
C
Lead Soldering Temperature, 10 seconds
300
C
Vapor Phase, 60 seconds
215
C
Infrared, 15 seconds
220
C
Power Dissipation (P
D
) T
A
= 25C
715
mW
Thermal Resistance, SO8 Junction to Case
JC
40
C/W
Thermal Resistance, SO8 Junction to Ambient
JA
140
C/W
Parameter
Conditions
Min.
Typ.
Max.
Unit
Supply Voltage V
CC
V
CC
to PGND
10
12
13.5
V
Ambient Temperature (T
A
)
0
85
C
Junction Temperature (T
J
)
0
125
C
5
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Electrical Specifications
V
CC
= 12V, and T
A
= 25C using the circuit in Figure 4 unless otherwise noted. The denotes specifications which
apply over the full operating temperature range.
Notes:
1.
All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control.
2.
Specifications guaranteed by design/characterization (not production tested).
3.
For propagation delays, "tpdh" refers to low-to-high signal transition and "tpdl" refers to high-to-low signal transition.
4.
Transition times are defined for 10% and 90% of DC values.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input Supply
VCC Voltage Range
V
CC
6.4
12
13.5
V
VCC Current
I
CC
OD = 0V
2.5
4
mA
OD Input
Input High Voltage
V
IH (OD)
2.5
V
Input Low Voltage
V
IL (OD)
0.8
V
Input Hysteresis
550
mV
Input Current
I
OD
OD = 3.0V
300
+300
nA
Propagation Delay
2
t
pdl(OD)
See Figure 5
25
40
ns
t
pdh(OD)
15
30
ns
PWM Input
Input High Voltage
V
IH(PWM)
3.5
V
Input Low Voltage
V
IL(PWM)
0.8
V
Input Current
I
IL(PWM)
-1
+1
A
High-Side Driver
Output Resistance, Sourcing
R
HUP
V
BOOT
V
SW
= 12V
2.5
3.3
Source Current
2
V
DS
= -10V
2.0
A
Output Resistance, Sinking
R
HDN
V
BOOT
V
SW
= 12V
1.1
1.5
Sink Current
2
V
DS
= 10V
3.0
A
Transition Times
2,4
t
R(HDRV)
Figure 4
25
40
ns
t
F(HDRV)
15
25
ns
Propagation Delay
2,3
t
pdh(HDRV)
See Figure 6
40
55
ns
t
pdl(HDRV)
25
40
ns
Low-Side Driver
Output Resistance, Sourcing
R
LUP
2.0
2.6
Source Current
2
V
DS
= -10V
2.7
A
Output Resistance, Sinking
R
LDN
0.9
1.2
Sink Current
2
V
DS
= 10V
3.5
A
Transition Times
2,4
t
R(LDRV)
Figure 4
20
30
ns
t
F(LDRV)
15
25
ns
Propagation Delay
2,3
t
pdh(LDRV)
See Figure 6
20
30
ns
t
pdl(LDRV)
15
25
ns
t
pdh(LDF)
See Adaptive Gate
Drive Circuit
description (page 10)
160
ns
6
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Figure 4. Test Circuit
Figure 5. Output Disable Timing
Figure 6. Adaptive Gate Drive Timing
FAN5109
1
2
3
4
8
7
6
5
HDRV
SW
PGND
LDRV
BOOT
PWM
OD
VCC
12V
33K
10K
3 nF
3 nF
1
F
V
IL(OD)
t
pdl(OD)
LDRV / HDRV
OD
t
pdh(OD)
V
IH(OD)
V
IH(PWM)
t
pdl (LDRV)
LDRV
PWM
HDRV-SW
1.3V
V
IL(PWM)
V
3
CC
t
pdl (HDRV)
t
pdh(LDRV)
t
pdh(LDF)
SW
t
pdh(HDRV)
7
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Typical Characteristics
Gate Drive Rise and Fall Times (1)
HDRV Rise/Fall Times vs. C
LOAD
HDRV Normalized Impedance vs. Temperature
Gate Drive Rise and Fall Times (2)
LDRV Rise/Fall Times vs. C
LOAD
LDRV Normalized Impedance vs. Temperature
0
5
10
15
20
25
30
35
40
0
1000
2000
3000
4000
5000
C
LOAD
(pf)
Ri
s
e
/F
al
l
T
i
m
e

(
n
s
ec)
Fall
Rise
RHDRV
(
n
o
r
m
a
l
i
z
e
d
)
0
5
10
15
20
25
30
35
40
0
1000
2000
3000
4000
5000
C
LOAD
(pf)
Ri
s
e
/
F
al
l
T
i
m
e

(
n
sec
)
Fall
0.8
0.9
1
1.1
1.2
1.3
1.4
-25
0
25
50
75
100
125
RL
DRV
(
n
o
r
m
a
l
i
z
e
d
)
Source
Sink
0.8
0.9
1
1.1
1.2
1.3
1.4
-25
0
25
50
75
100
125
Temperature (
C)
Temperature (
C)
Rise
Source
Sink
8
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Typical Performance Characteristics
(continued)
HDRV Pull-Up (Sourcing)
HDRV Pull-Down (Sinking)
LDRV Pull-Up (Sourcing)
LDRV Pull-Down (Sinking)
0
500
1000
1500
2000
2500
3000
0
2
4
6
8
10
12
0
2
4
6
8
10
12
0
2
4
6
8
10
12
0
2
4
6
8
10
12
VDS ( V)
ID
(
m
A
)
6 Vgs
8 Vgs
10 Vgs
12 Vgs
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
VDS ( V)
ID
(
m
A
)
6 Vgs
8 Vgs
10 Vgs
12 Vgs
0
500
1000
1500
2000
2500
3000
VDS (V)
ID
(m
A
)
6 Vgs
8 V gs
10 Vgs
12 Vgs
VDS (V)
ID
(
m
A
)
6 Vgs
8 Vgs
10 Vgs
12 Vgs
9
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Typical Performance Characteristics
(continued)
Negative SW Voltage Transient
Operating Current vs. Frequency
I
CC
[mA] = V
CC
(0.26 + 3.38 F
SW
) where F
SW
is in MHz
Negative LDRV Voltage Transient
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
0
100
200
300
400
500
Transient Duration (nsec)
Transient Duration (nsec)
VS
W
(
V
)
SOA
0
5
10
15
20
25
30
35
0
100
200
300
400
500
Frequency (KHz)
Ic
c (m
A
)
6 Vcc
12 Vcc
15 Vcc
-6.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
0
100
200
300
400
500
VL
DRV
(
V
)
SOA
SOA
10
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Circuit Description
The FAN5109 is a driver optimized for driving N-channel
MOSFETs in a synchronous buck converter topology. A
single PWM input signal is all that is required to properly
drive the high-side and the low-side MOSFETs.
For a more detailed description of the FAN5109 and its
features, refer to the Typical Application Diagram (Figure 1)
and Functional Block Diagram (Figure 3).
Low-Side Driver
The FAN5109's low-side driver (LDRV) is designed to
drive ground referenced low R
DS(on)
N-channel
MOSFETs. The bias for LDRV is internally connected
between V
CC
and PGND. When the driver is enabled, the
driver's output is 180 out of phase with the PWM input.
When the FAN5109 is disabled (OD = 0V), LDRV is held
low.
High-Side Driver
The FAN5109's high-side driver (HDRV) is designed to
drive a floating N-channel MOSFET. The bias voltage for
the high-side driver is developed by a bootstrap supply
circuit, consisting of an external diode and bootstrap
capacitor (C
BOOT
) .
During start-up, SW is held at PGND, allowing C
BOOT
to
charge to V
CC
through the diode. When the PWM input
goes high, HDRV will begin to charge the high-side
MOSFET's gate (Q1). During this transition, charge is
transferred from C
BOOT
to Q1's gate. As Q1 turns on,
SW rises to V
IN
, forcing the BOOT pin to V
IN
+V
C(BOOT)
,
which provides sufficient V
GS
enhancement for Q1.
To complete the switching cycle, Q1 is turned off by pull-
ing HDRV to SW. C
BOOT
is then recharged to V
CC
when
SW falls to PGND.
HDRV output is in phase with the PWM input. When the
driver is disabled, the high-side gate is held low.
Adaptive Gate Drive Circuit
The FAN5109 embodies an advanced design that
ensures minimum MOSFET dead-time while eliminating
potential shoot-through (cross-conduction) currents. It
senses the state of the MOSFETs and adjusts the gate
drive, adaptively, to ensure they do not conduct simulta-
neously. Refer to "Gate Drive Rise and Fall Times" wave-
forms on page 7 for the relevant timing information.
To prevent overlap during the low-to-high switching tran-
sition (Q2 OFF to Q1 ON), the adaptive circuitry monitors
the voltage at the LDRV pin. When the PWM signal goes
HIGH, Q2 will begin to turn OFF after some propagation
delay as defined by t
pdl(LDRV)
parameter. Once the LDRV
pin is discharged below ~1.3V, Q1 begins to turn ON
after adaptive delay t
pdh(HDRV)
.
To preclude overlap during the high-to-low transition (Q1
OFF to Q2 ON), the adaptive circuitry monitors the volt-
age at the SW pin. When the PWM signal goes LOW, Q1
will begin to turn OFF after some propagation delay
(t
pdl(HDRV)
). Once the SW pin falls below ~V
CC
/3, Q2
begins to turn ON after an adaptive delay t
pdh(LDRV)
.
Additionally, V
GS
of Q1 is monitored. When V
GS(Q1)
is
discharged below ~1.3V, a secondary adaptive delay is
initiated, which results in Q2 being driven ON after
t
pdh(LDF)
, regardless of the SW state. This function is
implemented to ensure C
BOOT
is recharged after each
switching cycle, particularly for cases where the power
convertor is sinking current and the SW voltage does not
fall below the V
CC
/3 adaptive threshold. Secondary delay
t
pdh(LDF)
is longer than t
pdh(LDRV)
.
Application Information
Supply Capacitor Selection
For the supply input (V
CC
) of the FAN5109, a local
ceramic bypass capacitor is recommended to reduce the
noise and to supply the peak current. Use at least a 1F,
X7R or X5R capacitor. Keep this capacitor close to the
FAN5109's V
CC
and PGND pins.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C
BOOT
) and an external diode, as shown in Figure 1.
These components should be selected after the high-
side MOSFET has been chosen. The required capaci-
tance is determined using the following equation:
where Q
G
is the total gate charge of the high-side
MOSFET, and
V
BOOT
is the voltage droop allowed on
the high-side MOSFET drive. For example, the Q
G
of the
FDD6696 MOSFET is about 35nC @ 12V
GS
. For an
allowed droop of ~300mV, the required bootstrap capaci-
tance is 100nF. A good quality ceramic capacitor must be
used.
The average diode forward current, I
F(AVG)
, can be esti-
mated by:
where F
SW
is the switching frequency of the controller.
The peak surge current rating of the diode should be
checked in-circuit, since this is dependent on the equiva-
lent impedance of the entire bootstrap circuit, including
the PCB traces.
Layout Considerations
Use the following general guidelines when designing
printed circuit boards (see Figure 7 on the next page):
1. Trace out the high-current paths and use short, wide
(>25 mil) traces to make these connections.
2. Connect the PGND pin of the FAN5109 as close as
possible to the source of the lower MOSFET.
C
BOOT
Q
G
V
BOOT
----------------------
=
(1)
I
F AVG
(
)
Q
GATE
F
SW
=
(2)
11
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
3. The V
CC
bypass capacitor should be located as close
as possible to V
CC
and PGND pins.
4. Use vias to other layers when possible to maximize
thermal conduction away from the IC.
Figure 7. Recommended layout for
SOIC-8 package (not to scale)
1
2
3
4
8
7
6
5
C
BOOT
C
VCC
12
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
Mechanical Dimensions
0.150, 8 Lead SOIC Package
8
5
1
4
D
A
A1
ccc C
LEAD COPLANARITY
SEATING
PLANE
e
B
L
h x 45
C
E
H
A
.053
.069
1.35
1.75
Symbol
Inches
Min.
Max.
Min.
Max.
Millimeters
Notes
A1
.004
.010
0.10
0.25
.020
0.51
B
.013
0.33
C
.0075
.010
0.20
0.25
E
.150
.158
3.81
4.01
e
.228
.244
5.79
6.20
.010
.020
0.25
0.50
H
.050 BSC
1.27 BSC
h
L
.016
.050
0.40
1.27
0
8
0
8
3
6
5
2
2
N
8
8

ccc
.004
0.10
D
.189
.197
4.80
5.00
Notes:
1.
2.
3.
4.
5.
6.
Dimensioning and tolerancing per ANSI Y14.5M-1982.
"D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
"L" is the length of terminal for soldering to a substrate.
Terminal numbers are shown for reference only.
"C" dimension does not include solder finish thickness.
Symbol "N" is the maximum number of terminals.
C
13
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
F
AN5109 Dual Bootstrapped 12V MOSFET Driver
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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