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Электронный компонент: FAN8036L

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2003 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.1
Features
4-CH Balanced Transformerless (BTL) Driver
1-CH (Forward Reverse) Control DC Motor Driver
Operating Supply Voltage (4.5V ~ 13.2V)
Built in Thermal Shut Down Circuit (TSD)
Built in Channel Mute Circuit
Built in Power Save Mode Circuit
Built in TSD Monitor Circuit
Built in 2 Regulators
Built in 2-OP AMPs
Description
The FAN8036 is a monolithic integrated circuit suitable for
a 5-CH motor driver which drives the tracking actuator,
focus actuator, sled motor, spindle motor, and tray motor of
the CDP/CAR-CD/DVDP systems.
48-QFPH-1414
Typical Application
Compact Disk Player
Video Compact Disk Player
Car Compact Disk Player
Digital Video Disk Player
Ordering Information
Device
Package
Operating Temperature
FAN8036L
48-QFPH-1414
-35
C ~ +85C
FAN8036_NL 48-QFPH-1414
-35
C ~ +85C
FAN8036
5-CH Motor Driver + 2-Regulator
FAN8036
2
Pin Assignments
OUT1
IN1-
FIN
(GND)
FIN
(GND)
48
47
46
45
43
44
42
41
40
39
37
38
6
5
4
3
1
2
12
11
10
9
7
8
13
14
15
16
18
17
19
20
21
22
24
23
25
26
27
28
30
29
IN2+
IN2-
OUT2
RES1
REGVCC
REGCTL
IN3+
IN3-
OUT3
IN4+
FIN
(GND)
IN4-
OUT4
CTL
FWD
REV
MUTE123 MUTE4
TSD_M PVCC2
DO5-
DO5+
PGND2
DO4-
DO4+
DO3-
DO3+
31
32
33
34
36
35
REGO2
REGO1
PGND1
DO2-
DO2+
DO1-
FIN
(GND)
DO1+
PVCC1
OPOUT2
OPIN2-
OPIN2+
VREF
SVCC
OPOUT1
OPIN1-
OPIN1+
IN1+
SGND
RES2
FAN8036
PS
FAN8036
3
Pin Definitions
Pin Number
Pin Name
I/O
Pin Function Descrition
1
IN1
-
I
CH1 OP-AMP Input (
-)
2
OUT1
O
CH1 OP-AMP Output
3
IN2+
I
CH2 OP-AMP Input (+)
4
IN2
-
I
CH2 OP-AMP Input (
-)
5
OUT2
O
CH2 OP-AMP Output
6
RES1
I
Regulator1 Reset
7
RES2
I
Regulator2 Reset
8
REGCTL
I
Regulator2 Control Voltage
9
IN3+
I
CH3 OP-AMP Input (+)
10
IN3
-
I
CH3 OP-AMP Input (
-)
11
OUT3
O
CH3 OP-AMP Output
12
IN4+
I
CH4 OP-AMP Input (+)
13
IN4
-
I
CH4 OP-AMP Input (
-)
14
OUT4
O
CH4 OP-AMP Output
15
CTL
I
CH5 Motor Speed Control
16
FWD
I
CH5 Forward Input
17
REV
I
CH5 Reverse Input
18
SGND
-
Signal Ground
19
MUTE123
I
Mute for CH1,2,3
20
MUTE4
I
Mute for CH4
21
PS
I
Power Save
22
TSD-M
O
TSD Monitor
23
PVCC2
-
Power Supply Voltage 2 (for CH3,CH4,CH5)
24
DO5
-
O
CH5 Drive Ouptut (
-)
25
DO5+
O
CH5 Drive Output (+)
26
PGND2
-
Power Ground 2 (for CH3,CH4,CH5)
27
DO4
-
O
CH4 Drive Ouptut (
-)
28
DO4+
O
CH4 Drive Output (+)
29
DO3
-
O
CH3 Drive Ouptut (
-)
30
DO3+
O
CH3 Drive Output (+)
31
REGO2
O
Regulator2 Ouptut
32
REGO1
O
Regulator1 Ouptut
FAN8036
4
Pin Definitions
(Continued)
Pin Number
Pin Name
I/O
Pin Function Descrition
33
PGND1
-
Power Ground 1 (for CH1, CH2)
34
DO2
-
O
CH2 Drive Ouptut (
-)
35
DO2+
O
CH2 Drive Output (+)
36
DO1
-
O
CH1 Drive Ouptut (
-)
37
DO1+
O
CH1 Drive Output (+)
38
PVCC1
-
Power Supply Voltage 1 (for CH1, CH2)
39
REGVCC
-
Regulator Supply Voltage( Regulator1,2)
40
OPOUT2
O
Normal OP-AMP2 Output
41
OPIN2
-
I
Normal OP-AMP2 Input (
-)
42
OPIN2+
I
Normal OP-AMP2 Input (+)
43
VREF
I
Bias Voltage Input
44
SVCC
-
Signal & OPAMPs Supply Voltage
45
OPOUT1
O
Normal OP-AMP1 Output
46
OPIN1
-
I
Normal OP-AMP1 Input (
-)
47
OPIN1+
I
Normal OP-AMP1 Input (+)
48
IN1+
I
CH1 OP-AMP Intput (+)
FAN8036
5
Internal Block Diagram
MUTE4
MUTE123
OUT1
IN1-
FIN
(GND)
FIN
(GND)
48
47
46
45
43
44
42
41
40
39
37
38
6
5
4
3
1
2
12
11
10
9
7
8
13
14
15
16
18
17
19
20
21
22
24
23
25
26
27
28
30
29
PS
TSD_M
REGVCC
TSD
IN2+
IN2-
OUT2
RES1
REGCTL
IN3+
IN3-
OUT3
IN4+
FIN
(GND)
IN4-
OUT4
CTL
FWD
REV
MUTE123 MUTE4
TSD_M PVCC2
DO5-
DO5+
PGND2
DO4-
DO4+
DO3-
DO3+
31
32
33
34
36
35
REGO2
REGO1
PGND1
DO2-
DO2+
DO1-
FIN
(GND)
DO1+
PVCC1
REGVCC
OPOUT2
OPIN2-
OPIN2+
VREF
SVCC
OPOUT1
OPIN1-
OPIN1+
IN1+
SGND
S
W
M
S
C
+
-
D
D
REGVCC
RES2
REGVCC
REGVCC REGVCC
PS
FAN8036
6
Equivalent Circuits
Description
Pin No
Internal Circuit
BTL INPUT
&
OP AMP1 INPUT
48,3,9,12,47
1,4,10,13,46
OP AMP2 INPUT
41,42
VREF
43
BTL OP AMP OUT
OP AMP1 OUT
2,5,11,14,45
VCC
VCC
2K
2K
9
3
12
47
48
4
1
10
13
46
VCC
5K
5K
41
42
VCC
43
1K
1K
5K
VCC
VCC
VCC VCC
5
11
45
2
14
FAN8036
7
Equivalent Circuits
(Continued)
Description
Pin No
Internal Circuit
OP AMP2 OUT
40
MUTE123,4
19,20
CTL
15
TSD-M
22
0.05K
40
VCC
VCC
0.05K
VCC
50K
50K
20K
19
20
15
VCC
1K
39K
22
20k
FAN8036
8
Equivalent Circuits
(Continued)
Description
Pin No
Internal Circuit
PS
21
FWD,REV
16,17
BTL CH1,2,3,4
OUTPUT
27,28,29,30,
34,35,36,37
BTL CH5
OUTPUT
24,25
50K
50K
100k
21
VCC
VCC
16
30K
30K
17
30K
30K
VCC
7K
VCC
28
30
35
37
27
29
34
36
40K
vcc
parastic diode
freewheeling diode
vcc
parastic diode
freewheeling diode
VCC
7K
VCC
60K
25
24
FAN8036
9
Equivalent Circuits
(Continued)
Description
Pin No
Internal Circuit
REGO1,2
31,32
RES1,2
6,7
REGCTL
8
10K
39
31
REGVCC
32
10K
10K
50K
50K
6
7
VCC
2K
10K
8
VCC VCC
FAN8036
10
Absolute Maximum Ratings ( Ta=25
C)
Note:
1. When mounted on the PCB of which size is 114mm
76mm 1.6mm.
2. Power dissipation is derated with the rate of -24mW/
C for T
A
25
C.
3. Do not exceed P
D
and SOA.
Recommended Operating Conditions ( Ta=25
C)
Parameter
Symbol
Value
Unit
Maximum Supply Voltage
SVCC
MAX
18
V
PVCC1
18
V
PVCC2
18
V
REGVCC
18
V
Power Dissipation
P
D
3
note
W
Operating Temperature
T
OPR
-35 ~ +85
C
Storge Temperature
T
STG
-55 ~ +150
C
Maximum Output Current
I
OMAX
1
A
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating Supply Voltage
SV
CC
4.5
-
13.2
V
PV
CC1
SV
CC
-
13.2
V
PV
CC2
SV
CC
-
13.2
V
REGV
CC
7
-
13.2
V
3,000
2,000
1,000
0
0
25
50
75
100
125
150
175
Pd (mW)
Ambient temperature, Ta [
C]
FAN8036
11
Electrical Characteristics
(SV
CC
=5V, PV
CC1
= PV
CC2
= 8V, T
A
= 25
C, unless otherwise specified)
Note :
1. When the voltage at pin 39 goes below 0.5V, the power save circuit makes the main bias current sources stop operating. As
a result, the whole circuits are disable. ( The whole circuits mean the driver circuit, the input OP amp circuit, and the normal
OP amp circuit.)
2. Guaranteed field.(No EDS/Final test)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Quiescent Circuit Current
I
CC
Under no-load
-
20
-
mA
Power Save On Current
I
PS
*note1
Under no-load
-
-
1
mA
Power Save On Voltage
V
PSON
Pin21 = Variation
-
-
0.5
V
Power Save Off Voltage
V
PSOFF
Pin21 = Variation
2
-
-
V
Mute123 On Voltage
V
MON123
Pin19 = Variation
-
-
0.5
V
Mute123 Off Voltage
V
MOFF123
Pin19 = Variation
2
-
-
V
Mute4 On Voltage
V
MON4
Pin20 = Variation
-
-
0.5
V
Mute4 Off Voltage
V
MOFF4
Pin20 = Variation
2
-
-
V
BTL DRIVER CIRCUIT
Output Offset Voltage
V
OO
V
IN
= 2.5V
-100
-
+100
mV
Maximum Output Voltage1
V
OM1
R
L
= 10
, CH1,2
4.5
6.0
-
V
Maximum Output Voltage2
V
OM2
R
L
= 18
, CH3,4,5
5.5
6.5
-
V
Closed-loop Voltage Gain
A
VF
V
IN
= 0.1Vrms
16.8
18
19.2
dB
Ripple Rejection Ratio
*note2
RR
V
IN
= 0.1Vrms, f = 120Hz
-
60
-
dB
Slew Rate
*note2
SR
Square, Vout = 4Vp-p
1
2
-
V/
s
INPUT OPAMP CIRCUIT
Input Offset Voltage1
V
OF1
-
-10
-
+10
mV
Input Bias Current1
I
B1
-
-
-
400
nA
High Level Output Voltage1
V
OH1
-
4.4
4.7
-
V
Low Level Output Voltage1
V
OL1
-
-
0.2
0.5
V
Output Sink Current1
I
SINK1
R
L
= 50
1
2
-
mA
Output Source Current1
I
SOU1
R
L
= 50
1
2
-
mA
Common Mode Input Range1
*note2
Vicm1
-
-0.3
-
4.0
V
Open Loop Voltage Gain1
*note2
G
VO1
V
IN
=
-75dB
-
80
-
dB
Ripple Rejection Ratio1
*note2
RR1
V
IN
=
-20dB, f = 120Hz
-
65
-
dB
Common Mode Rejection Ratio1
*note2
CMRR1
V
IN
=
-20dB
-
80
-
dB
Slew Rate1
*note2
SR1
Square, Vout = 3Vp-p
-
1.5
-
V/
s
FAN8036
12
Electrical Characteristics
(Continued)
(SV
CC
= 5V, PV
CC1
= PV
CC2
= 8V, T
A
= 25
C, unless otherwise specified)
Note: Guaranteed field.(No EDS/Final test)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
NORMAL OP AMP CIRCUIT 1
Input Offset Voltage 2
V
OF2
-
-10
-
+10
mV
Input Bias Current 2
I
B2
-
-
-
400
nA
High Level Output Voltage 2
V
OH2
-
4.4
4.7
-
V
Low Level Output Voltage 2
V
OL2
-
-
0.2
0.5
V
Output Sink Current 2
I
SINK2
R
L
= 50
2
4
-
mA
Output Source Current 2
I
SOU2
R
L
= 50
2
4
-
mA
Common Mode Input Range 2
*note
Vicm2
-
-0.3
-
4.0
V
Open Loop Voltage Gain 2
*note
G
VO2
V
IN
=
-75dB
-
80
-
dB
Ripple Rejection Ratio 2
*note
RR2
V
IN
=
-20dB, f = 120Hz
-
65
-
dB
Common Mode Rejection Ratio 2
*note
CMRR2
V
IN
=
-20dB
-
80
-
dB
Slew Rate 2
*note
SR2
Square, Vout = 3Vp-p
-
1.5
-
V/
s
NORMAL OP AMP CIRCUIT 2
Input Offset Voltage 3
V
OF3
-
-15
-
+15
mV
Input Bias Current 3
I
B3
-
-
-
400
nA
High Level Output Voltage 3
V
OH3
-
3
3.8
-
V
Low Level Output Voltage 3
V
OL3
-
-
1.0
1.5
V
Output Sink Current 3
I
SINK3
R
L
= 50
10
-
-
mA
Output Source Current 3
I
SOU3
R
L
= 50
10
-
-
mA
Open Loop Voltage Gain 3
*note
G
VO3
V
IN
=
-75dB
-
80
-
dB
Ripple Rejection Ratio 3
*note
RR3
V
IN
=
-20dB, f = 120Hz
-
65
-
dB
Common Mode Rejection Ratio 3
*note
CMRR3
V
IN
=
-20dB
-
80
-
dB
Slew Rate 3
*note
SR3
Square, Vout = 3Vp-p
-
1.5
-
V/
s
TRAY DRIVE CIRTUIT
Input High Level Voltage
V
IH
-
2
-
-
V
Input Low Level Voltage
V
IL
-
-
-
0.5
V
Output Voltage 1
V
O1
PV
CC2
= 8V, V
CTL
= 3V,
R
L
= 45
-
6
-
V
Output Voltage 2
V
O2
PV
CC2
= 8V, V
CTL
= 1.5V,
R
L
= 10
-
3
-
V
Output Load Regulation
V
RL
V
CTL
=3V, I
L
=100mA
400mA
-
300
700
mV
Output Offset Voltage 1
V
OO1
V
IN
= 5V, 5V
-40
-
+40
mV
Output Offset Voltage 2
V
OO2
V
IN
= 0V, 0V
-40
-
+40
mV
FAN8036
13
Electrical Characteristics
(Continued)
(SV
CC
= 5V, PV
CC1
= PV
CC2
= 8V, T
A
= 25
C, unless otherwise specified)
Note: Guaranteed field.(No EDS/Final test)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
REGULATOR1 CIRCUIT(REGVCC=8V
)
Load regulation
V
RL1
I
L
=0
200mA
-80
0
0
mV
Line regulation
V
CC1
I
L
=200mA,V
=
7V
9V
-20
0
+30
mV
Regulator output voltage 1
V
REG1
I
L
=100mA
4.75
5.0
5.25
V
Regulator reset on voltage 1
Reson1
Pin6=Variation
-
-
0.5
V
Regulator reset off voltage 1
Resoff1
Pin6=Variation
2
-
SVCC
V
Ripple Rejection 1
*note
RR1
Vin=1Vp-p, f=120Hz
-
55
-
dB
REGULATOR2 CIRCUIT(REGVCC=8V
)
Load regulation
V
RL2
I
L
=0
200mA
-80
0
0
mV
Line regulation
V
CC2
I
L
=200mA,V
=
7V
9V
-20
0
+30
mV
Regulator output voltage 2 range
V
REG2R
I
L
=100mA
1.5
-
4.5
V
Regulator output voltage 2
V
REG2
I
L
=100mA,V
REGCTL
=0V
1.482 1.56 1.638
V
I
L
=100mA,V
REGCTL
=1.9V
3.135
3.3
3.465
V
Regulator reset on voltage 2
Reson2
Pin7=Variation
-
-
0.5
V
Regulator reset off voltage 2
Resoff2
Pin7=Variation
2
-
SVCC
V
Control Gain
G
REGCTL
-
0.75
0.95
1.15
V/V
Ripple Rejection 2
*note
RR2
Vin=1Vp-p, f=120Hz
-
55
-
dB
FAN8036
14
Application Information
1. Thermal Shutdown
The TSD circuit is activated at the junction temperature of 160
C and
deactivated at 135
C with the hysteresis of 25C. During the thermal
shutdown, the TSD circuit keeps all the output driver off.
2. CH Mute Function
When the mute pin is high, the TR Q1 is on and Q2 is off, so the bias
circuit is enabled. When the mute pin is low (GND), the TR Q1 is off
and Q2 is on, so the bias circuit is disabled.
During the mute on state, all the circuit blocks except for the variable
regulator remain off, and the low power quiescent state is established.
Truth table is as follows;
3. Power Save Function
When the pin21 is high, the TR Q3 becomes on and Q4 off, so the bias
circuit is enabled. When the pin21 is low (GND) , the TR Q3 becomes
off and Q4 is on, so the bias circuit is disabled.
During the power save on state, this function keeps all the circuit
blocks off, and the low power quiescent state is established.
Truth table is as follows;
4. TDS Monitor Function
Pin 22 is TSD monitor pin, which detects the state of the TSD block
and generates the TSD-monitor signal.
In the normal state Q5 is on, and Q6 is off. When the TSD block is
activated Q5 becomes off, and thus the voltage of pin22 keeps low.
Truth table is as follows;
Pin 19, 20
Mute
High
Mute-Off
Low
Mute-On
Pin21
Power Save
High
Power Save Off
Low
Power Save On
TSD Pin22
TSD Off
High
TSD On
Low
Output driver
Bias
Q0
SVCC
IREF
Hysteresis
R1
R2
R3
Ihys
Bias Blocks
(4-CH BTL)
Q1
Q2
SVCC
MUTE
20
19
M ain Bias
Q3
Q4
SVCC
21
Q5
Q6
SVCC
20K
VCC
R(external)
22
FAN8036
15
5. Focus, Tracking Actuator, Spindle, Sled Motor Drive Part
The Vref at pin 43 is for eliminating the dc components from the input signals and can set by an exteranl circuit.
The voltage gain from Vin to output is as follows ;
Where
V means just ac component.
The total input to output voltage gain is the sum of the input OP amp network gain and 18dB.
The output stage is the balanced transformerless (BTL) driver.
The bias voltage Vp is expressed as ;
M
10K
10K
10K
10K
40K
60K
62K
DO+
DO-
PVCC1(PVCC2)
40K
40K
40K
VREF
IN+
IN-
OUT
Vin
48
1
3
4
9
10
12
13
2
5
11
14
43
37
36
35
34
30
29
28
27
Vp
Vp
V
DP
+
-
Q
P
Vin
Vref
V
+
=
DOP
V
D
4 V
+
=
DON
V
D
4
V
=
Vout
DOP DON
8 V
=
=
Gain
20
Vout
V
-------------
log
20
8
log
18dB
=
=
=
V
P
PVCC1 V
DP
V
CESAT
Q
P
(
)
62k
60k 62k
+
--------------------------
V
CESAT
Q
P
+
=
PVCC1 V
DP
V
CESAT
Q
P
1.97
--------------------------------------------------------------------------
=
V
CESAT
Q
P
+
- - - - - - - - - - (1)
FAN8036
16
6. Tray, Changer,panel Motor Drive Part
Rotational direction control
The forward and reverse rotational direction is controlled by FWD (pin16) and REV (pin17) and the input conditions are as
follows;
Where Vp(Power reference voltage) is approximately 3.75V at PV
CC2
=8V according to equation (1).
Motor speed control (When SV
CC
=5V, PV
CC2
=8V)
- The maximum torque is obtained when the pin15(CTL) is open.
- If the voltage of the pin15 (CTL) is 0V, the motor will not operate.
- When the control voltage (pin15) is between 0 and 3.0V, the differential output voltage V(out1,out2) is about two times
of control voltage. The output gain is 6dB.
- When the control voltage is greater than 3.0V, the output voltage is saturated at the 6.0V because of the output swing
limitation.
INPUT
OUTPUT
FWD
REV
OUT 1
OUT 2
State
H
H
Vp
Vp
Brake
H
L
H
L
Forward
L
H
L
H
Reverse
L
L
-
-
Hign impedance
M
24
25
out 1
out 2
D
LEVEL SHIFT
M.S.C
S.W
D
CTL
IN
FWD
REV
IN
16
17
15
V(out1,out2)
V
CTL
0
6.0V
3.0V
FAN8036
17
7. Regulator1 Part
The output voltage of the regulator1 is fixed to 5V.
When power save on or TSD on, regulator1 is disabled.
Truth table is as follows;
RES1(Pin6) REGO1
HIGH
Active
LOW
Deactive
REGVCC
2.5V
RES1
REGO1
10K
10K
33uF
6
39
32
REGVCC
R1
R2
VREF1
FAN8036
18
8. Regulator2 Part
The output of the regulator2 is variable.
The input impedance of the REGCTL pin is 50k
.
The REGCTL input circuit is as follows;
The output voltage(VREGO2) is decided as follows;
When the REGCTL pin is connect to the ground or open, the regulator output voltage becomse1.56V.
When power save on or TSD on, regulator2 is disabled.
Truth table is as follows;
RES2(Pin7) REGO2
HIGH
Active
LOW
Deactive
R EG O 2
1.56V
4.2V
R E G C TL
0.3V
1.77V
G ain=0.95
REGVCC
2.5V
RES2
REGO2
10K
40K
33uF
7
39
31
REGVCC
8
REGCTL
R3
R4
VREF2
50K
VCC
8
REGCTL
R1
R2
FAN8036
95
.
0
)
56
.
1
(
2
+
=
REGCTL
V
V
VREGO
FAN8036
19
Test Circuits
DO2+
PGND1
REGO1
DO1-
DO2-
VREF
SVCC
OPIN1- OPOUT1
IN1+ OPIN1+
DO1+
OPOUT2
PS
OPIN2+ OPIN2-
PVCC1
OUT1
IN1-
IN2+
IN2-
OUT2
RES1
IN4+
REGVCC
REGCTL
RES2
IN3-
OUT3
CTL
SGND
IN4-
FWD
REV
OUT4
DO3+
DO3-
PGND2
DO4+
DO4-
DO5+
MUTE123
DO5-
TSD-M
MUTE4
PVCC2
1
2
3
4
5
6
48
47
46
45
44
43
42
40
39
38
41
37
36
35
34
33
32
31
30
28
27
26
29
25
13
14
15
16
17
18
19
21
22
23
20
24
7
8
9
10
11
12
FAN8036
OP-AMP
IN+
IN-
OUT
OP-AMP
IN+
IN-
OUT
OP-AMP
IN+
IN-
OUT
OP-AMP
IN+
IN-
OUT
VREF
VCC
RL1
RL2
RL3
RL4
RL5
OP-AMP
IN+
IN-
OUT
VCC
V
AC
V
PULSE
V
DC
V
A
RL
V
B
SW1
SW2
SW3
SW4
PVCC1
OP-AMP
IN+
IN-
OUT
OP-AMP
IN+
IN-
OUT
V
CTL
V
FWD
V
REV
IN3+
REGO2
V
REGCTL
PVCC2
V
RES2
V
RES1
IL1
IL2
REGVCC
V
MU123
V
MU4
V
PS
FAN8036
20
Typical Application Circuits 1
[Voltage control mode]
[SERVO PRE AMP]
VCC
PVCC2
M
M
FOCUS
TRACKIN
G
SPINDLE
TRAY
PVCC1
VREF FOCUS
INPUT
TRACKING
INPUT
SLED
INPUT
SPINDLE
INPUT
M SLED
SVCC
IN1-
OUT1
IN2+
IN2-
OUT2
RES1
FAN8036
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
RES2
REGCTL
IN3+
IN3-
OUT3
IN4+
IN4
-
OU
T4
CTL
FWD
REV
SG
N
D
MUT
E
12
3
MUT
E
4
PS
TS
D_
M
P
V
CC2
DO5
-
DO3+
DO3-
DO4+
DO4-
PGND2
DO5+
DO1-
DO2+
DO2-
PGND1
REGO1
REGO2
OP
IN2
+
OP
IN2
-
OP
OU
T2
RE
G
V
C
C
P
V
CC1
DO1
+
IN1
+
OP
IN1
+
OP
IN1
-
OP
OU
T1
SV
C
C
VR
E
F
1
2
3
4
5
6
7
8
9
10
11
12
REGO2
REGO1
[CONTROLLER]
TRAY
CONTROL
TRAY
INPUT
SPINDLE
MUTE
FOCUS
TRACKING
SLED
MUTE
TSD_M
POWER
SAVE
REG1
RESET
REG2
RESET
VCC
REGVCC
FAN8036
21
Typical Application Circuits 2
[
Differential PWM control mode
]
Notes:
Radiation pin is connected to the internal GND of the package.
M
REGO2
REGO1
VCC
VCC
PVCC2
M
FOCUS
TRACKING
SLED
SPINDLE
TRAY
PVCC1
SVCC
VREF FOCUS
INPUT
TRACKING
INPUT
SLED
INPUT
SPINDL
E
INPUT
IN1-
OUT1
IN2+
IN2-
OUT2
RES1
FAN8036
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
RES2
REGCTL
IN3+
IN3-
OUT3
IN4+
IN4
-
OU
T
4
CTL
FW
D
REV
SG
N
D
MUT
E
12
3
MUT
E
4
PS
TS
D_
M
P
V
CC2
DO5
-
DO3+
DO3-
DO4+
DO4-
PGND2
DO5+
DO1-
DO2+
DO2-
PGND1
REGO1
REGO2
OP
IN2
+
OP
IN2
-
OP
OU
T
2
REG
V
CC
P
V
CC1
DO1+
IN1+
OP
IN1
+
OP
IN1
-
OP
OU
T
1
SVC
C
VRE
F
1
2
3
4
5
6
7
8
9
10
11
12
M
[SERVO PRE AMP]
REGVCC
TRAY
CONTROL
TRAY
INPUT
SPINDLE
MUTE
FOCUS
TRACKING
SLED
MUTE
TSD_M
POWER
SAVE
[CONTROLLER]
REG1
RESET
REG2
RESET
FAN8036
22
Mechanical Dimensions
Package
#1
#48
(0.825)
17.20
0.30
(4.85)
0.10MAX
0.65
14.00
0.20
17.20
0.30
14.00
0.20
+
0.10
-0.05
0.30
0.80
0.20
0.10MAX
2.60
0.10
3.00MAX
0.00~0.25
0~8
+
0.10
-0.05
0.20
48-QFPH-1414
FAN8036
5/22/03 0.0m 001
Stock#DSxxxxxxxx
2003 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.