ChipFind - документация

Электронный компонент: FAN8048

Скачать:  PDF   ZIP

Document Outline

2004 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0
Features
H-Bridge PWM Driver
4 Channels direct PWM H-bridge drivers
Digital input and direct PWM output
Internal power switches
- ON state resistance : 2.0
(typ.), which value added
the upper and the lower switches
Synchronous DC-DC Converter
Built-in step up converter (VG converter)
Built-in two synchronous step up-down converter
Built-in short circuit protection
Internal Switches
- Power Switch : 0.4
(typ.) at 500mA
-. Synchronous-Rectifier Switch : 0.4
(typ.) at 500mA
Others
Built-in power-on reset circuit
Built-in battery charge circuit
Built-in voltage regulator control circuit
Built-in thermal shutdown (TSD) circuit
Buit-in channel mute circuit
Descripation
The FAN8048 is a monolithic integrated circuit suitable for a
4 channels direct PWM H-bridge driver which incorporates
two switch-mode step up-down converter with synchronous
rectification provides local microprocessor and servo IC
power in portable CD players and portable devices.
48-LQFP-0707
Typical application
Portable CD-MP3 player
Ordering Information
Device
Package
Operating Temp.
FAN8048
48-LQFP-0707
-30
C ~ +85C
FAN8048
2 DC-DC Converter & 4-CH PWM Motor IC
FAN8048
2
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
VG
RST
OFF
ON
SPRT
SPGND
PCT
CLK
SOFT
EA1O
EA1-
EA2O
EA2- VSYS2 USW2
DSW2 VIN
PGND
DSW1 PGND USW1 VSYS1 REG
DCIN
CH4F
CH4R
CH3F
CH3R
CH2F
CH2R
CH1
MUTE
DGND
CHGSW
CHGCON
CHGSEN
LG
PGND CH1+ CH1- CH2+ CH2- PVCC CH3+
CH3- CH4+ CH4- PGND
FAN8048
FAN8048
3
Pin Definitions
Pin Number
Pin Name
I/O
Pin Function Description
1
VG
-
Gate voltage for power MOSFET drive
2
RST
O
Power-on reset output
3
OFF
I
System-off signal input
4
ON
I
System-on signal input
5
SPRT
-
Short circuit protection delay time setting capacitor
6
SGND
-
Pre-driver ground
7
PCT
-
Triangular waveform pin
8
CLK
I
Clock input
9
SOFT
-
Soft start time setting capacitor of DC-DC converter 1 and 2
10
EA1O
O
Error amplifier output of DC-DC Converter1
11
EA1-
I
Error amplifier inverting input of DC-DC converter1
12
EA2O
O
Error amplifier output of DC-DC converter2
13
EA2-
I
Error amplifier inverting input of DC-DC converter2
14
VSYS2
-
Output of DC-DC converter2
15
USW2
-
DC-DCconvereter2 coil driving pin 1
16
PGND
-
Power ground
17
DSW2
-
DC-DC convereter2 coil driving pin 2
18
VIN
-
Input voltage of DC-DC coverter 1 and 2
19
DSW1
-
DC-DC convereter1 coil driving pin 2
20
PGND
-
Power ground
21
USW1
-
DC-DC convereter1 coil driving pin 1
22
VSYS1
-
Output of DC-DC converter1
23
REG
O
Regulator control output
24
DCIN
-
Adaptor power supply input pin
25
CHGSEN
I
Charger current sense Input
26
CHGCON
O
Charger control output
27
CHGSW
I
Charger mode switch input
28
DGND
-
Digital circuit ground
29
MUTE
I
Channel mute input
30
CH1
I
CH1 input pin
31
CH2R
I
CH2 reverse input pin
32
CH2F
I
CH2 forward input pin
33
CH3R
I
CH3 reverse input pin
34
CH3F
I
CH3 forward input pin
35
CH4R
I
CH4 reverse input pin
36
CH4F
I
CH4 forward input pin
37
PGND
-
Power ground
38
CH4-
O
Channel 4 negative output
39
CH4+
O
Channel 4 positive output
40
CH3-
O
Channel 3 negative output
41
CH3+
O
Channel 3 positive output
42
PVCC
-
Power supply for H-bridge driver
43
CH2-
O
Channel 2 negative output
44
CH2+
O
Channel 2 positive output
FAN8048
4
Pin Definitions
(Continued)
Pin Number
Pin Name
I/O
Pin Function Description
45
CH1-
O
Channel 1 negative output
46
CH1+
O
Channel 1 positive output
47
PGND
-
Power ground
48
LG
-
VG voltage up coil driving pin
FAN8048
5
Internal Block Diagram
PGND
PGND
CH1+
CH1-
CH2+
CH2-
CH3+
CH3-
CH4+
CH4-
47
PVCC
42
46
45
44
43
41
40
37
48
LG
PV
C
C
SOFT
SGND
H-
Brid
ge
4
33
CH2F
CH1
CHGCON
30
CLK
EA1-
REG
15
28
PV
CC
H-Bridge 3
PV
CC
H-Bridge 2
PV
CC
H-Bridge 1
6
21
22
19
25
S1
S2
S3
S4
18
34
36
32
Battery
Charger
Switch
Regulator
& Current
Control
26
OFF
ON
20
16
PCT
EAI2-
VG
EA2O
SPRT
PGND
EA1O
7
0.9V
OSC
31
CH4R
CH4F
CH3R
CH3F
CH2R
SYSTEM OFF
17
STEP UP/DOWN
CONVERTER 1
DSW1
Driver & Logic
USW1 VSYS1
DSW2
SYSTEM
Control
SYSTEM ON
USW2
VSYS2
S1
S4
S3
S2
PRE-DRIVER
VIN
Driver & Logic
STEP UP/DOWN
CONVERTER 2
PGND
3
3-State
Input
Control
CH3R
CH3F
CH2R
CH2F
CH1R
CH1F
14
10
11
5
35
4
13
D
R
V
1
CH4F
CH4R
9
29
12
23
24
DCIN
CHGSW
DGND
MUTE
RST
2
VSYS1
0.5V
8
0.9V
27
CHGSEN
39
38
VIN
VSYS2
VSYS1
FAN8048
6
Absolute Maximum Ratings (Ta = 25C)
Power Dissipation Curve (Air Condition = 0m/S)
Notes:
1. When mounted on 2mm
114.3mm
1.6mm PCB (FR-4 glass epoxy material).
2. Refer: EIA/ J SED 51-2 and EIA/ J SED 51-3
JSED51-2 : Integrated circuits thermal test method environmental conditions - Natural convection
JSED51-3 : Low effective thermal conductivity test board for leaded surface mount packages
3. Do not exceed PD and SOA(Safe Operating Area).
Recommended Operating Conditions (Ta = 25C)
Parameter
Symbol
Value
Unit
H-bridge driver supply voltage
PVCC
7
V
Predriver supply voltage
VG
12
V
Primary side input voltage of DC-DC converter
VIN
7
V
Output voltage of DC-DC converter1
VSYS1
7
V
Output voltage of DC-DC converter2
VSYS2
7
V
AC adapter supply voltage
VDCIN
12
V
H-bridge driver output current
I
O
500
mA
Power dissipation
PD
1.0
W
Operating temperature
T
OPR
-30 ~ +85
C
Stroage temperature
T
STG
-55 ~ +150
C
Parameter
Symbol
Min.
Typ.
Max.
Unit
H-bridge driver supply voltage
PVCC
1.2
2.4
4.5
V
Power supply of DC-DC converter
VIN
1.8
2.4
4.5
V
Output voltage of DC-DC converter1
VSYS1
2.0
-
3.6
V
Output voltage of DC-DC converter2
VSYS2
1.6
-
VSYS1
V
AC adaptor supply voltage
DCIN
5.0
7.0
10.0
V
0
0.25
0.5
0.75
1
1.25
1.5
1.75
0
25
50
75
100
125
150
Ambient Temperature []
SOA
P
D
[W]
FAN8048
7
Electrical characteristics
(PVCC=VIN=2.4V, VSYS1=VSYS2=2.7V, VG=7.0V, DCIN=0V, C
PCT
=470pF, Ta=25
C,unless otherwise specifid)
Parameter
Symbol
Conditions
Min. Typ. Max. Unit
CURRENT
PVCC quiescent current
I
PVCC
-
-
-
3.0
A
VIN operating current
I
VIN
VON = 0V
-
1.6
3.0
mA
DCIN operating current
I
DCIN
DCIN = 5V
-
-
1.0
mA
VG operating current1
I
VG
Non driving 4 channels
-
1.0
1.5
mA
VG operating current2 (Note1)
I
VG4CH
Driving by 4 channels
-
1.5
2.0
mA
VSYS1 operating current
I
VSYS1
-
3.0
5.0
mA
VSYS2 operating current
I
VSYS2
-
-
1.0
mA
SYNCHRONOUS DC-DC CONVERTER PART
VG CONVERTER PART
VG output voltage
V
VG
IVG=1mA
6.0
7.0
8.0
V
VG converter start voltage
V
VGST
VG=3
5V Sweep
3.3
3.9
4.5
V
Oscillation frequency
F
LG
VG=3.5V, VLG=5V
65
100
135
KHz
STEP UP/DOWN CONVERTER (COMMON))
VSYS voltage at voltage up mode
V
UP
VIN=2.0V, ISYS=100mA
2.58
2.7
2.82
V
VSYS Load Stability at voltage up
mode
V
UP
VIN=2.0V, ISYS=0 to 150mA
-30
1.0
30
mV
VSYS voltage at voltage down mode
V
DOWN
VIN=3.0V, ISYS=100mA
2.58
2.7
2.82
V
VSYS load stability at voltage down
mode
V
DOWN
VIN=3.0V, ISYS=0 to 150mA
-30
1.0
30
mV
VSYS output stability at voltage up/down
V
UPDW
V
UPDW
=V
UP
-V
DOWN
-30
0
30
mV
ERROR AMPLIFIER
Error amplifier threshold voltage
V
EINTH
-
0.86
0.9
0.94
V
Error amplifier output voltage
V
EOL
-
-
0.16
0.2
V
Error amplifier input current
I
EIN
VEI=0.8V
-1
0.1
1
A
Error amplifier source current
I
ESOURCE
VEO=0V, VEI=0V
150
-
-
A
Error amplifier sink current
I
ESINK
-
1
-
-
mA
VSYS1 OPTION CIRCUIT
Error amplifier1 short circuit
detection voltage
V
eos
SPRT=L
H
1.20 1.35 1.45
V
SPRT input current1
I
sprt1
VEI=0V, VSPRT=0V
-9
-6
-4
A
SPRT input current2
I
sprt2
OFF=VSPRT=0V
-16
-12
-8
A
SPRT threshold voltage
V
sprth
VPCT=0.3V, VEO=0.4V,VEI=0V,
DSW=H
L
0.4
0.5
0.6
V
SOFT input current
I
soft
VSOFT=0V
-13
-10
-7
A
SPRT/SOFT discharge reset voltage
V
dis
VSYS1=1.3
1.7V
VSPRT, VSOFT=L
H
1.30 1.48 1.62
V
Voltage in switching between the
starter and normal modes
V
stn
VSYS1=1.5
2.0 V,DSW=H L
1.70 1.84 1.95
V
Vstn hysterisis voltage (Note1)
V
sthys
VSYS1=1.5
2.0 V
100
200
300
mV
FAN8048
8
Electrical characteristics
(Continued)
(PVCC=VIN=2.4V, VSYS1=VSYS2=2.7V, VG=7.0V, DCIN=0V, C
PCT
=470pF, Ta=25
C,unless otherwise specifid)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
VSYS2 OPTION CIRCUIT
VSYS2 voltage at buck mode
operation
V
BUCK
VIN=2.4V, VSYS2=1.8V
ISYS2=100mA
-
1.8
-
V
Load stability of VSYS2 at buck
mode operation
V
LS
VIN=2.4V, VSYS2=1.8V
ISYS2=0
100mA
-30
0
30
mV
OSCILLATOR (PCT)
Source current
I
SOURCE
-
34
42
50
A
Sink current
I
SINK
-
11
14
17
A
Oscillation frequency1
F
OSC1
No CLK, At self oscillation
45
60
75
KHz
Oscillation frequency2
F
OSC2
CLK=88.2kHz,
At synchronization mode
85.2
88.2
91.2
KHz
Maximum duty ratio (Note1)
D
MAX
CLK=88.2kHz
75
%
OUTPUT SWITCHES
On resistance of upper switch
R
ONSWU
Switch A and D, ISYS=500mA
-
0.4
0.6
On resistance of lower switch
R
ONSWL
Switch B and C, ISYS=500mA
-
0.4
0.6
Leakage current of upper switch
I
LSWU
Switch A and D
-
0
2
A
Leakage current of lower switch
I
LSWL
Switch B and C
-
0
2
A
POWER-ON RESET
RST threshold voltage1
V
RST1
VIN=2.4V, VSYS2=1.0
1.8V
1.20
1.35
1.50
V
Hysteresis voltage1
V
RST1
VIN=2.4V, VSYS2=1.8
1.0V
40
70
100
mV
RST threshold voltage2
V
RST2
VSYS2=2.7V, VIN=1.0
1.8V
1.30
1.45
1.60
V
Hysteresis voltage2
V
RST2
VSYS2=2.7V, VIN=1.8
1.0V
50
80
110
mV
CONTROL INPUT
System-on threshold voltage
V
ONTH
VSYS1=VSYS2=0V
-
VIN -
0.65
V
System-on input low level voltage
V
ONL
VSYS1=VSYS2=0V
VIN -1.0
-
-
V
System-on input current
I
ON
VON=0V
6
16
26
A
System-off threshold voltage
V
OFFTH
-
VSYS1-
1.15
V
System-off input low level voltage
V
OFFL
-
VSYS1-
1.4
-
V
System-off input current
I
OFF
-
-85
-70
-55
A
H-BRIDGE PWM DRIVER PART
(CH1)
Out on Resistance
R
ON1
Top + bottom switches
-
2.0
3.0
Input Resistance
R
IN1
-
-
50
-
K
High level Input voltage
V
IH1
-
2.2
-
-
V
Low level Input voltage
V
IL1
-
-
-
0.5
V
Rising Time (Note1)
T
RISE1
-
-
0.2
-
s
Falling Time (Note1)
T
FALL1
-
-
0.2
-
s
Minimum Pulse Width (Note1)
T
MIN1
-
-
300
-
ns
FAN8048
9
Electrical characteristics
(Continued)
(PVCC=VIN=2.4V, VSYS1=VSYS2=2.7V, VG=7.0V, DCIN=0V, C
PCT
=470pF, Ta=25
C,unless otherwise specifid)
Notes:
1. Design reference value
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
(CH2,3,4)
Out on Resistance
R
ON
Top + bottom switches
-
2.0
3.0
Input Resistance
R
IN
-
-
30
-
K
High level Input voltage
V
IH
-
2.2
-
-
V
Low level Input voltage
V
IL
-
-
-
0.5
V
Rising Time (Note1)
T
RISE
-
-
0.2
-
s
Falling Time (Note1)
T
FALL
-
-
0.2
-
s
Minimum Pulse Width (Note1)
T
MIN
-
-
300
-
ns
CONTROL INPUT
Mute input high voltage
V
MUTEH
-
2.2
-
-
V
Mute input low voltage
V
MUTEL
-
-
-
0.5
V
REGULATOR AND CHARGER PART
Regulator output voltage
V
VIN
DCIN=6.5V, Ivin1=200mA
3.7
4.0
4.3
V
Line regulation of regulator
Vdc
DCIN=5V
7V,
Ivin1=200mA
-50
0
50
mV
Load regulation of regulator
Vrl
Ivin1=0
200mA
-40
0
10
mV
CHGON Current
Ichon
-
15
-
-
mA
Constant Charge Current
Ichg
Rs=1.1
400
450
500
mA
CHGSW-on high voltage
V
CHGSWH
-
2.0
-
-
V
CHGSW-on low voltage
V
CHGSWL
-
-
-
0.5
V
THERMAL SHUT DOWN
Operating temperature (Note1)
TSD
-
-
150
-
C
Thermal hysteresis (Note1)
T
HYS
-
-
20
-
C
FAN8048
10
Application Information
1. System Control and Protection Functions
1-1. System Enable/Disable Function
As shown in Figure 1, system enable ON (pin4) should be set low (typically under VIN - 0.65V) only once until OFF (pin3)
receives the disable signal (typically under VSYS1 - 0.85V), then all circuits remain in enable status.
Also, to prevent malfunction, this function activates when the circuit short condition exists such as over current or circuit
shorts, the whole circuit becomes the disable.
When the circuit is enabled, to obtain the necessary power (VG) to operate the internal circuits and upper side output power
switches of the 4 channels H-bridge driver, the VG converter circuit is activated. Also, to stably operate all circuits, the VG
converter keeps other circuits from activating until the output voltage of the VG converter reaches the specific voltage (3.9V).
When the output voltage of the VG converter reaches 3.9V, the first DC-DC converter (DC-DC Converter1) activate. And
when output voltage of DC-DC converter1(VSYS1) reaches 1.35V, the second converter (DC-DC Converter2) activates in
sequence. The circuit activation sequence as stated above and a flow chart are shown in Figure 3 and Figure 4.
1-2. Channel Mute Function
When MUTE (pin29) is high (typically above 2.2V), the mute circuit activates, so the all motor driver (4 channels H-bridge
driver) outputs are in mute state; on the other hand, when it is low (under 0.5V), mute state is off.
1-3. Thermal Shut Down(TSD) Function
This thermal shutdown (TSD) function is designed to protect the chip from being damaged as the chip's internal temperature
rises. If the TSD circuit activates, all motor driver (4 channel H-bridge drivers) outputs are in mute state. When the chip's
internal temperature reaches 150C (typical), then the TSD circuit is activated, and when the chip temperature falls to 130C or
below, the TSD circuit is deactivated and the output drivers operate normally.
Figure 1. Block Diagram of System Control Circuit
VG
ON
1
DC-DC Converter
Wake-up Singnal
Bias &
Refernece
VG Converter
DC-DC
Converter
System_ON
Vref1
Bias
R1
R2
4
Start_up
Circuit
System_ON
MUTE
150
125
TSD
Mute Circuit
29
Channel Mute
SPRT
OFF
EA1O
C
SPRT
1.35V
10
3
5
System_OFF
0.5V
VSYS1
Short Circuit Detector
6uA
12uA
22
VSYS1
VSYS1<1.65V
FAN8048
11
1-4. Power-On Reset (POR) Function
FAN8048 has two DC-DC converters to supply stable power to external circuits and components of the CD player set.
Therefore, for these output voltages of DC-DC converters to provide stable power to external circuits and their components,
the DC input voltage,VIN, and the output voltages of converter, VSYS1 and VSYS2, monitoring function is required.
The DC input voltage, VIN, and the output voltage of converter2 are individually divided by the internal resistors and then
compared with the internal 0.5V reference voltage, VREF2, to determine the low voltages condition.
This power on reset (POR) circuit is shown in Figure2.
Figure 2. Block Diagram of Power On Reset
1-5. Power Sequence
The following graph and flowchart of Figure 3 and Figure 4 show the power sequence of the VG converter and two DC-DC
converters (DC-DC converter1 and DC-DC Converter2); herein, VG converter generates power for internal circuits and upper
side output power switches of the 4 channels H-bridge driver, and the DC-DC converters supply the external circuits and com-
ponents.
Figure 3. Plot of Power Sequence
RST
Vref2
14
22
2
18
VSYS1
VSYS1
VSYS2
VIN
RST
V
SYS1
V
SYS2
V
RST
V
G
=7.0V
t
Voltage
3.9V
1.35V
Converter 1
Wake-up
Reset Signal
Hysteresis
Converter 2
Wake-up
FAN8048
12
Figure 4. Flow Chart of Power Sequence
Start
VG > 3.9V
SYSON
SYSOFF
VG Converter
Wake-up
Yes
No
VSYS2 > 1.35V
DC-DC Converter 1
Wake-up
SYSTEM OFF
Yes
Yes
Yes
SYSTEM READY
VSYS1 > 1.35V
DC-DC Converter 2
Wake-up
Yes
Yes
No
No
VSYS1 > 1.84V
Yes
No
EA1O < 1.35V
Time < Tsprt
No
Yes
SYSON = LOW
No
Yes
Start-up Mode
Normal Mode
FAN8048
13
2. H-Bridge Driver (CH1, CH2, CH3 and CH4 )
2-1. H-Bridge Driver for Actuators and Sled Motor (CH2, CH3 and CH4)
Channel 2, channel 3, and channel 4 have two inputs FWD and RVE and an H-bridge type of output to the forward or reverse
Sled motor and the Focus and Tracking actuator as shown in Figure 5. The H-bridge driver operation is as in the following log-
ical truth table below. That is, to forward or reverse, the output is the same as the input, and when the two input signals match,
the lower switching devices (switches B and C) are turned-on, Sled motor, Focus and Tracking actuator are in braking state.
Figure 5. Block Diagram of H-Bridge driver for CH2, CH3 and CH4
2-2. Logical Truth Table
2-3. H-Bridge driver for spindle motor (CH1)
Figure 6 shows spindle motor driver. The circuit consists of 3-states of input (High, Low, and High impedance) to perform for-
warding, reversing, and braking of the motor. The detailed operation is shown in logical truth table.
Figure 6. Block Diagram of H-Bridge driver for Spindle motor
2-4. Logical Truth Table
Note:
1. Z is high impedance input
FWD
REV
OUT+
OUT-
Function
L
L
L
L
Brake
L
H
L
H
Reverse
H
L
H
L
Forward
H
H
L
L
Brake
INPUT
MO1
MO2
CH+
CH-
Function
H
H
H
H
L
Forward
L
L
L
L
H
Reverse
Z
L
H
L
L
Brake
FWD
PVCC
43
44
A
B
C
D
32
31
Pr
edri
ver
VG
VSYS
VA
VB
VC
VD
REV
OUT+
OUT-
LOGIC AND PREDRIVER
PVCC
45
46
A
B
C
D
VG
VSYS
VA
VB
VC
VD
CH1
CH1+
CH1-
Pr
edrive
r
30
MO1
MO2
50K
LOGIC AND PREDRIVER
OUTPUT STAGE
VSYS1
50K
70K
60K
40K
80K
FAN8048
14
3. DC-DC Converter (VG Converter and Synchronous DC-DC Converter)
3-1. VG Converter (Step up Converter)
The VG converter is used to generate necessary power (VG) for upper side output power switches operation of 4 channels H-
bridge driver and other internal circuit operations as shown in Figure 7. The output voltage (VG) of VG converter is internally
set to 7.0V, and it activates DC-DC Converter 1 when VG converter output voltage reaches 3.9 V. Also VG converter has an
oscillator function, which is required for switching operations and to minimize external components.
Figure 7. Set up Converter (VG Converter)
3-2. Synchronous Step-up/Down Converter
The FAN8048 provides high efficiency and low noise power for applications such as portable instrumentation. Figure 8 shows
the functional block diagram of synchronous step up/down converter.
Figure 8. Block diagram of Step-up/down converter
In Figure 8, the output voltage (VSYS) of DC-DC converter is calculated as follows:
48
Clock
Sawtooth
Vref1
DC-DC Converter
Wake-up Singnal
R1
R2
SW
FAN8048
D1
L
G
V
BAT
C
G
SYSTEM_ON
1
4
ON
VG
LG
0.9V
R1
R2
11
R
C
C
C
Error Amp
10
V
Y
VA
VB
VC
VD
VA
VB
VD
VC
V
Z2
V
Z1
V
X
19
21
Power Stage
FAN8048 DC-DC Converter
V
BAT
USW
DSW
CLK
VSYS
8
PCT
9
SOFT
1.79V
Start Comp
VSYS
18
PCT
OSC2
L
ogi
c & predriver
7
Stop Comp
1.27V
0.5V
Start & Short Circuit Protection
Sync. Clock
SPRT
22
V
COM
V
COM
5
1.48V
PCT
OSC2
0.56V
C
P
]
[
9
.
0
,
]
[
)
2
1
1
(
V
V
where
V
R
R
V
V
REF
REF
SYS
=
+
=
FAN8048
15
3-3. Oscillator
Oscillator frequency is determined by the charging/discharging current i
CG
and i
DCG
of the internal circuit and capacitor
(C
PCT
) connected to PCT (pin7) and ground. To change oscillator frequency, you may change the C
PCT
capacitor.
For example, the external capacitor (C
PCT
) value can be calculated as follows:
Where, i
CG
is charging current, which is 42uA, i
DCG
is discharging current, which is 14uA, and oscillator peak-peak voltage,
V
PCT
is approximately 300mV. This oscillator is designed to synchronize the frequency of the oscillator itself to the clock
pulse frequency separately input to external CLK (pin8). To utilize this function, the oscillator frequency itself should be con-
figured lower than the frequency of the external synchronous signal.
3-4. Error Amplifier
The error amplifier of the DC-DC converter is used to amplify the difference between internal reference voltage and output
voltage. This amplified voltage generates a square wave pulse corresponding to the difference of triangular waveform-PCT
output formed by triangular wave oscillatory circuit of pulse width modulation comparator (PWM comparator), whereby the
square wave pulse stabilizes the output voltage by operating the DC-DC converter's switching devices through the operation
circuit. The most well-known system stabilization method using an error amplifier is pole-zero compensation. Detailed system
design standards and methods will be discussed in a later section of this document.
3-5. Short Circuit Protection Function
The short circuit protection is a function to protect circuits from being damaged from various abnormal conditions such as over
current or circuit shorts; and on this occasion, when the error amplifier output voltage, EIO1, (pin10) of DC-DC converter1
reaches the specific voltage (typically 1.35V), the internal current source, i
SPRT
, start charging the external capacitor, C
SPRT
connected between SPRT(pin5) and ground as shown in Figure 1 and the DC-DC converter circuit will be shutdown. Also, to
prevent malfunction, this function activates only when the circuit short condition exists for a certain amount of time. This time
setting (T
SPRT
) is determined according to the capacitance of external capacitor C
SPRT
, and its formula is as follows:
Where, i
SPRT
is charging current, which is 6uA.
3-6. Soft Start
This function limits overshoot in the initial operation. This circuit operates when DC-DC converter 1 output voltage rises over
a specific voltage (typically 1.48V), thereafter it starts charging the external capacitor C
SOFT
connected between SOFT (pin9)
and Ground. It restricts the error amplifier output voltage caused by sharp-rising capacitor voltage. Soft start time is deter-
mined by the following formula:
When the output voltage of the conveter, VSYS1, is brought above typically 1.48V, the soft start function is enable and the
internal current source is begin to charging the capacitor, C
SOFT
. A detailed diagram of this fuction is shown in Figure 8. The
component C
SOFT
provide a slow ramping voltage on the SOFT pin to provide a soft start function. The time constant in this
case is shown by the next formular.
where, i
SOFT
= 10uA
)
i
(i
V
f
i
i
C
)
i
(i
V
C
i
i
t
f
i
i
)
i
(i
V
C
i
V
C
i
V
C
t
DCG
CG
PCT
PCT
DCG
CG
PCT
DCG
CG
PCT
PCT
DCG
CG
PCT
PCT
DCG
CG
DCG
CHG
PCT
PCT
DCG
PCT
PCT
CG
PCT
PCT
PCT
+
=
+
=
=
+
=
+
=
1
[sec]
5
.
0
SPRT
SPRT
SPRT
i
C
T
=
[sec]
10uA
C
i
C
T
SOFT
SOFT
SOFT
SOFT
=
=
FAN8048
16
3-7. Operation mode of Step-up/down converter
Figure 9 shows the connection of the four internal output power switches, external Inductor, and input/output voltage, which
are components of the FAN8048 built-in DC-DC converter.
As shown in Figure 10, the DC-DC converter determines a switching operation mode (Buck, Buck-Boost and Boost) according
to the relationship between control voltage VX and VY and oscillator output voltage V
PCT
. Also, the DC-DC converter indi-
cates the different operational statuses of output power switch (Output switches, A, B, C, and D) according to operational
mode. Herein, control voltage VX is the output voltage of error amplifier, and voltage VY is level shift voltage in VX.
Figure 9. Simplified Diagram of Output Swiches
Figure 10. Switching control vs. internal control voltages, V
X
and V
Y
VA
VB
VD
VC
19
USW
VIN
18
22
21
A
B
C
D
DSW
VSYS
Boost Mode
Buck/Boost Mode
Buck Mode
Duty
Switch A ON B OFF
PWM CD Swiches
Four Switches PWM
Switch D ON C OFF
PWM AB Swiches
0%
V
X
> V
PCT
V
X
> V
Y
V
Y
> V
PCT
V
Y
> V
X
V
X
V
PCT
V
Y
V
PCT
D
MAX_BOOST
D
MIN_BOOST
D
MAX_BUCK
75%
FAN8048
17
3-8. Buck(Step-down) converter mode (VIN > VSYS)
The step-down converter keeps the average output voltage VSYS lower than DC input voltage VIN all the time. Figure 11-a
shows a conceptual circuit diagram of the step-down converter in case an electrical load is pure resistance. Herein, all switch-
ing devices are supposed to be at ideal conditions and instantaneous output voltage VSYS is dependent on the status of switch-
ing devices. That is, the input/output of the step-down converter is obtained by the following formula according to the Volt-Sec
balance condition and each waveform is shown in Figure.11-b, where D means duty cycle. In this formula, since duty ratio D
is smaller than 1.0, average output voltage VSYS is always displayed in the lower range of the DC input voltage.
where, D is duty cycle.
In practical application circuits, there are several drawbacks as follows:
(1) As most practical circuits are not exposed to pure electrical resistance loads, but to inductive loads and because of the stray
inductive there is the switch would have dissipate the inductive energy and therefore it may be destroyed. .
(2) This is not the case of most application circuit, but when output voltage fluctuates between zero and power voltage VIN, a
low pass filter composed of an inductor and capacitor is required to minimize the output voltage ripple.
Figure 12 shows the operation waveform of internal control voltage VX and VY and output power switching devices in Step-
down converter mode. When the internal control voltage VY is higher than control voltage VX and triangular waveform
V
PCT
, switch D is always turned-on and switch C is always turned-off in step-down converter mode. The switching operation
of switch A is activated by the signal generated by comparison between internal control VX and triangular waveform voltage
V
PCT
. Also, synchronous switch B remains turned-on during synchronous switch B turn-off time. That is, in step-down con-
verter mode, switch A and B always activate in opposite switching operations. The peak-peak ripple voltage (
VSYS) of out-
put voltage is calculated using the following formula:
Where,
I
L
is the inductor current from Figure11 (b) during turn-off (t
OFF
).
The value of the output capacitor to reduce output voltage ripple is calculated using the following formula.
The average value of the inductor current at boundary between continuos and discontinuous conduction mode is
where,
So to obtain the inductor value using the above formula, the redefined formula is as follows:
]
[
1
V
V
D
V
IN
SYS
=
S
ON
T
T
D
=
S
SYS
S
S
L
O
O
SYS
T
D
L
V
C
T
T
I
C
C
Q
V
)
1
(
8
2
2
2
1
1
-
=
=
=
S
SYS
L
T
D
L
V
I
)
1
(
-
=
2
)
1
(
8
S
SYS
SYS
S
T
D
V
V
L
T
C
-
=
)
(
2
2
1
,
SYS
IN
S
peak
L
LB
V
V
L
DT
i
I
-
=
=
]
[V
D
V
V
SYS
IN
=
min
,
2
)
1
(
O
S
SYS
I
T
D
V
L
-
=
FAN8048
18
(a)
(b)
Figure 11. Synchronous Step-down Converter
Figure 12. Switches operation waveforms during Buck Converter mode
A
D
V
A
V
B
B
R
VSYS
VIN
C
V
C
t
V
L
Ton
Ts
Toff
(V
IN
-V
SYS
)
VSYS
A
B
0
t
i
L
=I
O
0
(-V
IN
)
V
A
V
B
V
C
V
D
High
Low
V
X
V
Y
PCT
FAN8048
19
3-9. Buck-Boost (Step-down/up) Converter Mode (VIN = VSYS)
As shown in Figure.13-a, the synchronous buck-boost converters take the mixed form of step-up and step-down converters.
That is, in case switching devices in the series connection of the two converters activate in the same duty ratio, the input/output
relationship during normal conditions can be expressed as follows: Namely, the output voltage VSYS can be higher or lower
than DC input voltage VIN according to duty ratio D.
As shown in Figure 13-b, the current flowing through the inductor is constant in continuous conduction mode. And the input
and output voltages relationship formula can be defined as follows, because , the integral of the inductor voltage over one time
period to zero.
Assuming a lossless circuit, input and output power are the same (Pin=Po) and the above formula can be redefined as follows:
As you can see in Figure 14, when internal control voltage VX and VY remain in the triangular waveform voltage V
PCT
range,
the converter acts as a step-up or step-down converter mode according to DC input voltage VIN and electrical load VSYS and
ISYS status. As displayed in Figure13-a, in this operation mode all four switching devices of the output terminal activate upon
operational mode step-up or step-down. Figure13-b shows the operational waveform of each section in this activation mode.
]
[
1
V
V
D
D
V
IN
SYS
-
=
D
D
V
V
T
D
V
DT
V
IN
SYS
S
SYS
S
SYS
-
=
=
-
-
+
1
0
)
1
)(
(
D
D
I
I
IN
SYS
-
=
1
FAN8048
20
(a)
(b)
Figure 13. Synchronous Step-up/down Converter
Figure 14. Output switches operation and waveforms at Buck/Boost (Step-up/down) mode
V
A
V
B
V
C
V
D
A
B
C
D
R
VIN
VSYS
t
V
L
Ton
Ts
Toff
(-V
SYS
)
VSYS
A
B
0
t
i
L
=I
IN
0
(V
IN
)
V
A
V
B
V
C
V
D
V
X
V
Y
PCT
FAN8048
21
3-10. Boost (Step-up) converter mode (VIN < VSYS)
The step-up converter keeps the average output voltage VSYS higher than DC input voltage VIN, and its circuit diagram is
shown in Figure 15-a. Figure 15-b shows an operational waveform in case inductor current is steady-state. Since in steady-
state, the integral of the inductor voltage over one time period to zero, this can be expressed by the following formula:
From the above formula, a redefined formula is as follows after dividing by cycle Ts:
Assuming a lossless circuit, input and output power are the same (Pin=Po) and the above formula can be redefined as follows:
This can be expressed as follows using input/output current and duty ratio:
In the boundary condition of continuous mode and discontinuous mode, the inductor's average current is defined as follows:
From the above formula, since inductor current and input current are the same (i
IN
=i
L
), the average output current at the edge
of continuous conduction mode can be redefined as below:
In a practical synchronous step-up converter, the parasitic elements are due to the loss associated with the inductor, the capaci-
tor and the switches; however, in this formula we assume that all components are at ideal conditions.In the continuous mode,
as the output current and peak-peak voltage ripple are considered to be constant, this formula can be redefined as below:
Where,
0
)
)
((
)
(
=
-
+
OFF
SYS
IN
IN
t
V
V
t
V
ON
]
[
1
1
1
1
V
V
D
V
D
t
T
V
V
IN
SYS
OFF
S
IN
SYS
-
=
-
=
=
O
SYS
IN
IN
I
V
I
V
=
)
1
(
D
I
I
IN
O
-
=
2
,
)
1
(
2
2
1
2
1
D
D
L
V
T
T
L
V
i
i
SYS
S
ON
IN
peak
L
LB
-
=
=
=
2
)
1
(
2
D
D
L
V
T
I
SYS
S
OB
-
=
C
DT
R
V
C
DT
I
C
Q
V
S
SYS
S
O
SYS
=
=
=
RC
DT
V
V
S
SYS
SYS
=
]
[
=
O
SYS
I
V
R
FAN8048
22
In Figure 16, when control voltage VX is always higher than VY and triangular waveform voltage V
PCT
, Switch pairs C and D
will alternately switching and their circuit is designed to operate as a step-up converter, whose output voltage is always higher
than input voltage. Figure 15 shows the operational waveform at the output terminal of each switching device when it acts as a
step-up converter. In this operations section, Switch A is always turned-on and switch B is always turned-off. Also, to limit the
maximum output voltage in this mode, the maximum duty ratio is limited to about 75%.
(a)
(b)
Figure 15. Synchronous Step-up Converter
Figure 16. Output switch operational waveforms in Boost (Step-up) converter mode
D
A
B
C
R
VIN
VSYS
V
B
V
C
V
D
t
V
L
Ton
Ts
Toff
(V
IN
-V
SYS
)
VSYS
A
B
0
t
i
L
0
(V
IN
)
V
A
V
B
V
C
V
D
High
Low
V
X
V
Y
PCT
FAN8048
23
3.10.1 Effect of Parasitic Elements in Step-up Converter
In a practical synchronous step-up converter, the parasitic elements are due to the loss associated with the inductor, the capaci-
tor and the switches; however. Figure 17 qualitatively show the effect of these parasitics on the voltage transfer ratio. Unlike
the ideal characteristic, in paractice VSYS/VIN declines as the duty ratio approaches unity. Because of very poor switch utili-
zation at high values of duty ratio, the curves in this range are show as dotted.
Figure 17. Effect of parasitic elements on voltage conversion ratio
D
0
IN
SYS
V
V
1
Ideal
D
-
1
1
Due to parasitic
elements
FAN8048
24
3.11 Component of Error Amplifier Compensation Network
In this chapter, we would like discuss the method of converter error amplifier design to control voltage mode PWM. In general,
a negative feedback control circuit composed of error amplifier using an operational amplifier and comparator is often used to
stabilize output voltage in switching mode converters. Controller design standards and methods for a stable system are as fol-
lows:
(1) To reduce regulation error of the output voltage, the loop gain crossover frequency, f
C,
should be as high as possible.
(2) To obtain stable phase margin, let the slope gain at 0dB be -20dB/dec. That is, have the gain phase at 0dB close to -90.
(3) Set the loop gain crossover frequency, f
C
be set to 1/5 ~ 1/10 of the switching frequency f
S
.
But in boost converter, due to the RHP zero, f
RHPZ
, the loop gain frequency, fC, must be designed well below the RHP
zero because the boost converter have a right half plane (RHP) zero. ( f
C
=f
RHPZ
/10)
(4) Set compensation pole, f
P1
to cancel the ESR zero f
FILTER_ZERO
. (f
P1
= f
FILTER_ZERO
)
(5) Place a high-frequency compensator pole, f
P2
to get the maximum attenuation of the switching ripple and high frequency
noise the minimum phase lag at f
C
.
(6) Place a two compensator zeroes, f
Z1
and f
Z2
below f
C
. Place the fz1 below the power stage natural frequency,
f
FILTER_POLE
to avoid a conditional stability. When setting these two zeroes (fz1 and fz2), converter performance and sta-
bility margin should be considered.
(7) Select the compensator parameters. (R's and C's )
To meet the design standards mentioned above, Figure 18 shows circuits and the characteristics of a typical compensator,
which has a controller structure with two zeroes (fz1 and fz2) and poles (fp1 and fp2).
First of all to design an error amplifier, natural frequency of system, f
FILTER_POLE
and ESR zero using an equivalent series
resistance of the output capacitor can be obtained by the following formula.
Double poles by the output filter are obtained from the following formula:
Where, Co is the output capacitor.
The ESR zero by the output capacitor, C
O
and equivalent series resistance of the output capacitor, R
ESR
can be obtained by the
following formula.
where, R
ESR
is the equivalent series resistance of output filter capacitor.
Figure 18. Error Amplifier Compensation Circuit
]
[
2
1
_
Hz
LC
f
O
POLE
FILTER
=
]
[
2
1
_
Hz
C
R
f
O
ESR
ZERO
FILTER
=
Phase
Gain
-20dB/dec
= -2slop
-20dB/dec
= -2slop
20dB/dec
= +2slop
+90
o
-90
o
0
o
Av1
Av2
f1
f2
f3
f4
VSYS
R1
R4
C1
11
10
0.9V
Error Amp
R2
R3
C3
C2
Note
C
1
>>C
3
R1>>R3
Vc
FAN8048
25
A troublesome feature in boost converter mode is the right-half plan (RHP) zero, and is given by:
.Most applications demand an improved transient response to allow a smaller output filter capacitor, and to achieve a higher
bandwidth, type 3 compensation is required. In Figure 18, pole and zero of the error amplifier are expressed as follows:
And because it has C1 >> C3 and R1 >> R3 in general, it can be simplified as below:
]
[
2
2
Hz
L
I
V
f
O
IN
RHPZ
=
]
[
3
1
3
1
2
2
1
]
[
2
3
2
1
]
[
)
3
1
(
2
2
1
]
[
1
2
2
1
]
[
)
3
1
(
1
2
1
2
1
2
1
Hz
C
C
C
C
R
f
Hz
C
R
f
Hz
R
R
C
f
Hz
C
R
f
Hz
C
C
R
f
P
P
Z
Z
I
+
=
=
+
=
=
+
=
]
[
3
2
2
1
]
[
2
3
2
1
]
[
2
1
2
1
]
[
1
2
2
1
]
[
1
1
2
1
2
1
2
1
Hz
C
R
f
Hz
C
R
f
Hz
C
R
f
Hz
C
R
f
Hz
C
R
f
P
P
Z
Z
I
=
=
=
=
=
FAN8048
26
3-12. Considerations of Input and Output Capacitors in DC-DC converter
Input Capacitors
The input capacitor is necessary to minimize the peak current drawn from the battery. Typically a several ten times uF tantalum
capacitor is recommending. Low equivalent series resistance (ESR) capacitors will help to minimize battery voltage ripple.
Output Capacitors
Low ESR capacitors should be used at the output of the DC-DC converter to minimize output ripple. The high frequency
switching speeds and fast changes in the output capacitor current, mean that the equivalent impedance of the capacitor can con-
tribute greatly to the output ripple. In order to minimize these effects choose an output capacitor with less than 10nH of equiv-
alent series inductance (ESL) and less than 100mW of equivalent series resistance (ESR). Typically these characteristics are
met with ceramic capacitor, but may also be met with certain types of tantalum capacitor. For a step change of load, the output
filter inductor in Figure 19 acts as a source of constant current during in this load transient, and the change in load current as a
transient is supplied by the filter capacitor. Hence, following a load transient,
3-13. Layout and Ground Considerations
High frequency switching and large peak currents means PCB design for DC-DC converters requires careful consideration. A
general rule is to place the DC-DC converter circuitry well away from any sensitive RF or analog components. The layout of
the DC-DC converters and its external components are also based on some simple rules to minimize EMI and output voltage
ripple.
Layout
1. Place all power components, FAN8048, inductor, input capacitor and output capacitor as close together as possible.
2. Keep the output capacitor as close the FAN8048 as possible with very short traces to the VSYS and GND pins.
3. Keep the external feedback loop network as close the FAN8048 as possible with very short traces, but away from the four
channels output as far as possible.
Grounding
1. Use a star grounding system with separate traces for the power ground and the low power signals such as ON/OFF and
MUTE. The star should radiate from where the power supply enters the PCB.
2. On the multilayer boards use components side copper for grounding around the FAN8048 and connect back to a quiet
ground plane using vias.
Figure 19. ESR in the output capacitor
SYS
SYS
I
ESR
V
-
=
L
ESR
C
R=Load
i
L
Output Filter
V
SYS
i
SYS
FAN8048
27
4. Series Voltage Regulator and Battery Charger Function
As shown in Figure 20, if the external adaptor supplies high voltage (in general, adaptor voltage used for portable devices is
above 4.5V), the series voltage regulator is internally designed to be 4V so as to be suitable for circuit operation; and when
necessary, it has the function of battery charging using an external adaptor.
4.1 Non-charging mode (Series Voltage Regulator Function)
When battery-charging mode is unnecessary, CHGSW (pin27) input may be LOW. On this occasion, the output voltage VREG
(Voltage on pin18) of the series voltage regulator is internally designed to be 4.0V.
When DCIN(pin24) is not supplied (when VIN is connected from the batteries), this circuit is need diode(D1) for prevent the
VIN (Volatege on pin18) leakage current can not flow in to the IC.
The related formula for this is expressed as follows:
4.2 Charging mode (Battery Charger function)
To charge the battery using an external adaptor, CHGSW ( pin27) input should be HIGH. In charging mode, internal transistor
Q1 and external transistor Q3 are turned-on to connect the battery with the external adaptor.
On this occasion, charging current,
i
CHG
can be determined by current detection resistance Rs, and charging current is
obtained by the following formula:
Figure 20. Block Diagram of Regulator and Battery charger
]
[
4
)
5
.
0
)
2
1
1
((
,
1
V
V
R
R
V
SAT
Q
REG
=
-
+
=
]
[
5
.
0
A
R
I
S
CHG
=
0.5V
23
CHGCON
18
26
27
Charge_ON
DCIN
R1
R2
R
S
DCIN
VIN
REG
CHGSW
25
24
Adaptor
CHGSEN
Q3
i
CHG
Q2
Q1
DC-DC
Converter
D1
FAN8048
28
5. Precaution
1. Attach a de-coupling capacitor between power supply pins and ground.
2. Check that the following items will not result while this IC is in use, or otherwise the IC will be broken or burned with
smoke generated.
-. Short-circuiting between output pins
-. Short-circuiting between output and ground pins
-. Short-circuiting between output and power supply pins
-. Reverse insertion of IC
The following pins are all output pins.
VG(pin1), RST(pin2), EA1O(pin10), EA2O(pin12), VSYS2(pin14), USW2(pin15), DSW2(pin17), DSW1(pin19),
USW1(pin21), VSYS1(pin22), REG(pin23), CHGCON(pin26), CH4-(pin38), CH4+(pin39), CH3-(pin40), CH3+(pin41),
CH2-(pin43), CH2+(pin44), CH1-(pin45) and CH1+(pin46)
The following pins are all ground pins.
SGND(pin6), PGND(pin16), PGND(pin20), DGND(pin28), PGND(pin37) and PGND(pin47)
The following pins are all power supply pins.
VIN(pin18), DCIN(pin24) and PVCC(pin42)
Note)
This document provides reference information on the use of this IC, which does not, however, guarantee the proper oper-
ation of any applications employing this IC. Constantly or values provided in this document are reference values and not
guaranteed values.
FAN8048
29
Typical Performance Characteristics
Temperature vs Ivin
0
0.5
1
1.5
2
2.5
3
-35
-15
5
25
45
65
85
Temperature []
Ivi
n
[mA]
Temperature vs fosc
50
55
60
65
70
75
80
-35
-15
5
25
45
65
85
Temperature []
fo
sc

[
KH
z
]
Temperature vs flg
50
70
90
110
130
150
-35
-15
5
25
45
65
85
Temperature []
fl
g [K
H
z
]
Temperature vs Ivg
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
-35
-15
5
25
45
65
85
Temperature []
I
vg[
mA]
Temperature vs Idcin
0
0.2
0.4
0.6
0.8
-35
-15
5
25
45
65
85
Temperature []
Idcin [m
A
]
Temperature vs Vvg
5
6
7
8
9
-35
-15
5
25
45
65
85
Temperature []
Vvg
[V]
FAN8048
30
Typical Performance Characteristics
VIN vs VSYS
2.5
2.6
2.7
2.8
2.9
1.8
2.1
2.4
2.7
3
3.3
3.6
3.9
4.2
4.5
VIN [V]
VSYS [
V
]
VSYS1
VSYS2
Temperature vs Vup
2.55
2.6
2.65
2.7
2.75
2.8
2.85
-35
-15
5
25
45
65
85
Temperature []
Vup[V]
Vup1
Vup2
Temperature vs Vdown
2.55
2.6
2.65
2.7
2.75
2.8
2.85
-35
-15
5
25
45
65
85
Temperature []
Vd
own
[
V
]
Vdown1
Vdown2
DCIN vs VIN(Regulator Output)
3.7
3.8
3.9
4
4.1
4.2
4.3
4.5
5.5
6.5
7.5
8.5
9.5
DCIN(V)
VI
N(V
)
FAN8048
31
Typical Performance Characteristics
(Continued)
Output Switches Rdson of DC-DC Converter1
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0
50
100
150
200
250
300
350
400
450
I_load[mA]
Rd
son
[]
Rdsw_Upper
Rdsw_Low
Rusw_Upper
Rusw_Low
Output Switches Rdson of DC-DC Converter2
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0
50
100
150
200
250
300
350
400
450
I_load[mA]
Rd
so
n
[]
Rdsw_Upper
Rdsw_Low
Rusw_Upper
Rusw_Low
Output Switches Rdson of Channel 1
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
0
50
100
150
200
250
300
350
400
450
I_load[mA]
R
d
son[
]
Ron1+_hi
Ron1+_lo
Ron1-_hi
Ron1-_lo
Output Switches Rdson of Channel 2
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
0
50
100
150
200
250
300
350
400
450
I_load[mA]
Rd
so
n
[]
Ron2+_hi
Ron2+_lo
Ron2-_hi
Ron2-_lo
Output Switches Rdson of Channel 3
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
0
50
100
150
200
250
300
350
400
450
I_load[mA]
Rd
s
o
n[
]
Ron3+_hi
Ron3+_lo
Ron3-_hi
Ron3-_lo
Output Switches Rdson of Channel 4
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
0
50
100
150
200
250
300
350
400
450
I_load[mA]
R
d
s
on[
]
Ron4+_hi
Ron4+_lo
Ron4-_hi
Ron4-_lo
FAN8048
32
Typical Application Circuits
FAN8048
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
C3
C4
C2
C6
C5
R1
C7
R2
C8
R3
R4
R5
R6
C10
R7
Q1
B
a
tte
r
y
R8
R9
Q2
DCIN
DCGND
L2
L3
VBATT
VSYS2
VSYS1
VBATT
C1
D1
L1
Tracking
Focus
Sled
Spindle
MUTE
CHGSW
F
R
F
R
F
R
Servo Amp & Controller
SYSTEM ON
SYSTEM OFF
RESET
CLOCK
SOFT
SGND
CLK
EA1-
OFF
ON
PCT
VG
EA2O
SPRT
EA1O
RST
REG
EAI2-
PGND
DSW1
USW1
VSYS1
DSW2
USW2
VSYS2
VIN
PGND
DCIN
CH2F
CH1
CHGCON
CH4R
CH4F
CH3R
CH2R
CHGSW
DGND
MUTE
CHGSEN
PGND
PGND
CH1+
CH1-
CH2+
CH2-
CH3+
CH3-
CH4+
CH4-
PVCC
LG
CH3F
C9
C11
D2
FAN8048
33
Package Dimensions
48-LQFP-0707
FAN8048
1/8/04 0.0m 001
Stock#DSxxxxxxxx
2004 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.