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April 2005

FAN8741/FAN8742 Rev. 1.0.1

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FAN8741/FAN8742

Spindle Motor and 6-CH Driver

[Spindle(PWM), Sled 2-CH(PWM) 4-CH(Linear)]

Features

Common

· Built-in thermal shutdown circuit (TSD)

· 8 Independent voltage sources

· Corresponds to 3.3V or 5V DSP

· 4 selectable mute inputs

Spindle

· Output PWM mode control

· FG output: open collector type

· Selectable brake(short & reverse brake)

· Built-in hall bias

· 180

commutation(compatible with conventional BLDC spindle

motor)

· Built in short-through protection function

BTL(Sled 2-channels)

· Output PWM mode control

· Built in short-through protection function

BTL(Other 4-channels)

· Output linear mode control

Typical Applications

· CD-ROM

· CD-RW

· DVD-ROM

· DVD-RAM

· DVD Player (DVDP)

· Other compact disk media

· Game consoles

Description

Suitable for a 3-phase BLDC (Brush-Less Direct Current) spindle
motor driver with PWM, the monolithic FAN8741/FAN8742 IC also
includes 2-ch motor drivers with PWM for sled motors and 4-ch
linear drivers which drive the focus actuator, tracking actuator, tilt
actuator, and loading motor in optical media applications.
Designed specifically for high-speed/high-density optical media
applications, the FAN8741/FAN8742's power stage is created by
D-MOS transistors which have extremely low RDS

. This

enables less heat generation and guarantees improved reliability.

The FAN8741G/FAN8742G is available in a 56-SSOP-HS pack-
age, which has high-power dissipation and the leadframe is
exposed to the top side.

The FAN8741MTF/FAN8742MTF is available in a 56-TSSOP-EP
package, which is very thin and the leadframe is exposed to
the bottom side.

Ordering Information

HS=HeatSlug, EP=ExposedPad

X:Tape & Reel type

FAN8741:FG3X
FAN8742:FG1X

Device

Package

Operating Temp.

FAN8741G

56-SSOP-HS

C to +75

FAN8741GX

56-SSOP-HS

C to +75

FAN8742G

56-SSOP-HS

C to +75

FAN8742GX

56-SSOP-HS

C to +75

FAN8741MTF

56-TSSOP-EP

C to +75

FAN8741MTFX

56-TSSOP-EP

C to +75

FAN8742MTF

56-TSSOP-EP

C to +75

FAN8742MTFX

56-TSSOP-EP

C to +75

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Internal Block Diagram

(Pins numbered according to the FAN8741MTF--Leadframe exposed to the bot

tom)

H-bridge

DIR

OSC

Hall Amp

Com

utator

& Pow

r dr

ive

Reverse Detect

r
egue

e
r
a
t
o
r

i
n
dl

r
e
c
t
i
o
n

OMAX

Drive
Logic

Flip

Flop

OSC

PWM Control

10k

Lev

h
i
f
t

20k

10k

BTL driver

BTL

driver

BTL

driver

BTL

driver

g
e

p
&

scil

l
a
t
or

VCP

REF

PWM Control

OSC

bridge

PWM Control

Hall bias

Mute Selection

&Spindle brake sel.

TSD

29
30

2
3

50
51

27
28

HU+

HV+

HW+

VM1

RSP2

RSP1

PGND2
PGND1

SPIN

REF

VM2

RSL1

SL1+

SL1

PGND3

RSL2

SL2+

SL2

SLIN2

SLIN1
SVCC2

SGND

MUTE1

MUTE2

SVCC1

DGND

VDD

VCP

CP2

CP1

IN3

IN4

PVCC3

DO4

DO4+

PGND5

PVCC2

DO3

DO3+

PVCC1

DO2

DO2+

DO1+

DO1

PGND4

IN1
IN2

VCP

LPF

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Pin Assignments

(Leadframe exposed to the bottom side)

FAN8741MTF/

SPIN

VDD

IN3

IN4

PGND5

DO4-

PVCC3

DO3+

DO2-

DO2+

DO1-

DO1+

DO4+

DO3-

IN1

PVCC1

PVCC2

SLIN1

SLIN2

PGND4

IN2

DIR

SVCC1

CP1

CP2

VCP

VM1

HU-

HV+

HV-

HW+

HW-

DGND

HU+

PGND1

RSP1

PGND2

RSP2

SL1-

SL2+

SL2-

PGND3

REF

SL1+

MUTE1

MUTE2

RSL1

RSL2

VM2

SVCC2

SGND

FAN8742MTF

(PAD DOWN)

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Pin Assignments

(Leadframe exposed to the top side)

FAN8741G/

SPIN

VDD

IN3

IN4

PGND5

DO4-

PVCC3

DO3+

DO2-

DO2+

DO1-

DO1+

DO4+

DO3-

IN1

PVCC1

PVCC2

SLIN1

SLIN2

PGND4

IN2

DIR

SVCC1

CP1

CP2

VCP

VM1

HU-

HV+

HV-

HW+

HW-

DGND

HU+

PGND1

RSP1

PGND2

RSP2

SL1-

SL2+

SL2-

PGND3

REF

SL1+

MUTE1

MUTE2

RSL1

RSL2

VM2

SVCC2

SGND

FAN8742G

(SHOULD THIS

SAY "PAD UP"

TO MATCH THE
PREVIOUS PAGE?)

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Pin Definitions

Pin Number

(exposed to bottom)

Pin Number

(exposed to top)

Pin Name

I/O

Pin Function Description

VM1

Power supply for spindle

HU+

Hall signal input(Hu+)

HU-

Hall signal input(Hu-)

HV+

Hall signal input(Hv+)

HV-

Hall signal input(Hv-)

HW+

Hall signal input(Hw+)

HW-

Hall signal input(Hw-)

Hall bias

PGND1

Power ground 1 for spindle channel

3-phase output U for spindle

RSP1

Spindle current sensing 1

3-phase output V for spindle

PGND2

Power ground 2 for spindle channel

3-phase output W for spindle

RSP2

Spindle current sensing 2

SL1+

Sled channel 1 drive output +

SL1-

Sled channel 1 drive output -

SL2+

Sled channel 2 drive output +

SL2-

Sled channel 2 drive output -

PGND3

Power ground for sled channels

REF

Reference voltage input

MUTE1

Mute input 1

MUTE2

Mute input 2

RSL1

Sled current sensing 1

RSL2

Sled current sensing 2

VM2

Power supply for sled

SVCC2

Power supply for BTL Pre driver

SGND

Signal ground for BTL signal block

SLIN2

Sled channel 2 input

SLIN1

Sled channel 1 input

PVCC2

Power supply for BTL CH3

PVCC1

Power supply for BTL CH1/2

IN2

Channel 2 input

IN1

Channel 1 input

PGND4

Power ground for BTL CH1/2

DO1 +

Channel 1 drive output +

DO1 -

Channel 1 drive output -

DO2 +

Channel 2 drive output +

DO2 -

Channel 2 drive output -

DO3 +

Channel 3 drive output +

DO3 -

Channel 3 drive output -

PVCC3

Power supply for BTL CH4

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Pin Definitions(continued)

Pin Number

(exposed to bottom)

Pin Number

(exposed to top)

Pin Name

I/O

Pin Function Description

DO4 +

Channel 4 drive output +

DO4 -

Channel 4 drive output -

PGND5

Power ground for BTL CH3/4

IN4

Channel 4 input

IN3

Channel 3 input

VDD

Power supply for digital block

SPIN

Spindle channel input

DIR

Spindle rotational direction output

Spindle frequency generator

FAN8741MTF=3X, FAN8742MTF=1X

SVCC1

Power supply for signal block

CP1

Charge pump capacitor1

CP2

Charge pump capacitor2

VCP

Charge pumped voltage

DGND

Ground for digital block

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Absolute Maximum Ratings (Ta = 25

NOTE

Parameter

Value

Unit

Supply Voltage (Signal block)

Supply Voltage (Digital block)

Supply Voltage (Spindle/Sled/BTL/BTL pre driver)

Power

issipation (56-TSSOP-EP)

1.6 / 3.2 / 4.1

Power

issipation (56-SSOP-HS)

3.1 / 4.7

Operating Temperature Range

-20 to +75

Storage

emperature Range

-40

to +150

Maximum Output Current (Spindle)

2.0

Maximum Output Current (CH1/2/3/4, Sled)

1.0

56-TSSOP-EP, Case 1

56-TSSOP-EP, Case 2

Remark

Pd is mea-

sured base on

the JEDEC/

STD(JESD

51-2)

Pd=1.6 W

Pd=3.2 W

56-TSSOP-EP, Case 3

Pd=4.1 W

56-SSOP-HS, Case 1

56-SSOP-HS, Case 2

Pd=3.1W

Pd=4.7W

soldering

Power plane(Cu)

VIA hole

GND plane(Cu)

Power plane(Cu)

soldering

PCB(glass-epoxy)

Power

plane(Cu)

GND plane(Cu)

PCB(glass-epoxy)

GND plane(Cu)

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1. 56-TSSOP-EP, Case 1: Single layer PCB with 1 signal plane only, PCB size is 76mm

114mm

1.6mm.

2. 56-TSSOP-EP, Case 2: Multi layer PCB with 1 signal, 1 power and 1 ground planes, PCB size is 76mm

114mm

1.6mm, Cu

plane sizes for power and ground is 74mm

62mm

0.035mm. Down pad of IC is soldered on the PCB.

3. 56-TSSOP-EP, Case 3: PCB condition is same to case 2 except via holes, which penetrate PCB all layers. Down pad of IC is sol-

dered on the PCB.

4. 56-SSOP-HS, Case 1: Single layer PCB with 1 signal plane only, PCB size is 76mm

114mm

1.6mm.

5. 56-SSOP-HS, Case 2: Multi layer PCB with 1 signal, 1 power and 1 ground planes, PCB size is 76mm

114mm

1.6mm, Cu

plane sizes for power and ground is 74mm

62mm

0.035mm.

6. Power dissipation is reduced by -12.8mW/

C for using above Ta=25

C in 56-TSSOP-EP, case 1.

7. Power dissipation is reduced by -25.6mW/

C for using above Ta=25

C in 56-TSSOP-EP, case 2.

8. Power dissipation is reduced by -32.8mW/

C for using above Ta=25

C in 56-TSSOP-EP, case 3.

9. Power dissipation is reduced by -24.8mW/

C for using above Ta=25

C in 56-SSOP-HS, case 1.

10. Power dissipation is reduced by -37.6mW/

C for using above Ta=25

C in 56-SSOP-HS, case 2.

11. Do not exceed P

and SOA (Safe Operating Area).

Power Dissipation Curve

Recommended Operating Conditions (Ta = 25

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage (Spindle Signal block)

4.5

5.5

Supply Voltage (Digital block)

4.5

5.5

Supply Voltage (Spindle driver)

4.5

13.2

Supply Voltage (Sled driver)

4.5

13.2

Supply Voltage (BTL driver)

4.5

CC2

Supply Voltage (BTL signal block)

4.5

13.2

Output current(Spindle)

1.0

1.5

Output current(Focus, Tracking, Loading)

0.5

0.8

Output current(Sled)

0.5

0.8

100

125

150

175

Ambient temperature, [

Power dissipation, [W]

SOA

56-SSOP-HS,case2

56-TSSOP-EP,case3

56-TSSOP-EP,case2

56-SSOP-HS,case1

56-TSSOP-EP,case1

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ELECTRICAL CHARACTERISTICS (Ta = 25

(Ta=25

C, SVCC1=VDD=PVCC1=VM2=5V,VM1=SVCC2=PVCC2=PVCC3=12V unless otherwise noted)

* : Design guarantee specification

Parameter

Condition

Min. Typ. Max. Units

COMMON PART

Quiescent Circuit Current 1

Mute1=L, Mute2=L

Quiescent Circuit Current 2

Mute1=L, Mute2=H

1.5

9.5

Quiescent Circuit Current 3

Mute1=H, Mute2=H

Mute Low Voltage

MUTE=variation

0.8

Mute High Voltage

MUTE=variation

3.0

Mute Input Current

MUTE=5V

130

Charge Pump Voltage 1

PUMP

=0mA

Charge Pump Voltage 2

PUMP

=-1mA

THERMAL SHUTDOWN

Operating Temperature*

150

Hysteresis Temperature*

SPINDLE DRIVE PART

Control Input Deadzone11

SPIN>VREF

100

Control Input Deadzone12

SPIN<VREF

-100

-50

-20

Control Voltage Input Range

Output Gain

MSP

/RCS

RCS

=0.33

=1[V/V]

2.55

3.0

3.45

A/V

Output On Resistance(upper)

Io=500mA

0.4

Output On Resistance(lower)

Io=500mA

0.4

Output Limit Current

RCS

=0.33

1.5

Hall Amp Common Mode Input Range -

Minimum Hall Input Level*

Hall Bias Output Voltage

=10mA

0.5

1.0

1.5

Hall Bias Input Current

FG Low Voltage

=3mA

0.5

DIR Low Voltage

DIR

=3mA

0.5

SLED DRIVE PART

Control Input Deadzone21

SLIN1/SLIN2 > VREF

Control Input Deadzone22

SLIN1/SLIN2 < VREF

-30

-15

Output Gain

MSL

/RCS

RCS

=1[V/V]

0.85

1.0

1.15

A/V

Output On Resistance(upper)

Io=250mA

1.0

Output On Resistance(lower)

Io=250mA

1.0

Output Limit Current

RCS

0.5

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ELECTRICAL CHARACTERISTICS (Ta = 25

C, continued)

(Ta=25

C, SVCC1=VDD=PVCC1=VM2=5V,VM1=SVCC2=PVCC2=PVCC3=12V unless otherwise noted)

Parameter

Condition

Min.

Typ.

Max.

Units

CH1,CH2 DRIVE PART (TYPICALLY ACTUATOR DRIVER)

Output Saturation Voltage H

=500mA

0.5

Output Saturation Voltage L

=500mA

0.5

Closed Loop Voltage Gain

16.5

19.5

Output Offset Voltage

VREF=IN1=IN2=1.65V

-50

CH3,CH4 DRIVE PART (TYPICALLY TILT,LOADING DRIVER)

Output Saturation Voltage H

=500mA

1.0

Output Saturation Voltage L

=500mA

0.5

Closed Loop Voltage Gain

16.5

19.5

Output Offset Voltage

VREF=IN3=IN4=1.65V

-50

CH1,CH3 GAIN DIFFERENCE SPEC (TYPICALLY FOCUS,TILT DRIVER)

CH1-CH3 Gain Difference

VFT12

- G

VFT34

-0.5

0.5

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Equivalent Circuits

(Pins numbered according to FAN8741MTF)

Charge Pump Outputs

FG/DIR Outputs

Spin Input

Hall Inputs

Hall Bias Input

Mute1 & 2 Inputs

Spindle Drive Outputs

Spindle Current Sensing Input

SVCC2

SVCC1

50
51

10K

SVCC1

Ref

SVCC1

60K

SVCC1

40K

22
23

SVCC2

VM1

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Equivalent Circuits(continued)

(Pins numbered according to FAN8741MTF)

Sled 1 & 2 Inputs

Sled Drive Outputs

CH1/2/3/4 (BTL Channels) Inputs

Sled 1 & 2 Current Sensing Inputs

Reference Input

CH4 Outputs

CH3 Outputs

CH1 & 2 Outputs

10K

SVCC2

Ref

24 25

16 18

17 19

10K

SVCC2

Ref

VM2

SVCC2

SVCC2 PVCC3

SVCC2 PVCC2

SVCC2 PVCC1

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Application Information

1. Torque Control & Output Current Control of 3-phase Bldc Motor

1) By amplifying the voltage difference between V

REF

and SPIN from Servo IC(or DSP), the Torque AMP produces the input

voltage(V

AMP

) which means input current command.

2) The output current (I

) is converted into the voltage (V

) through the sense resistor (R

) and compared with the V

AMP

3) The clock generator always make the RS latch become set periodically, this enables the output driver's on state, when the V

and the V

AMP

are equal the state becomes off.

4) By the negative feedback loop, the sensed output voltage V

equals to the V

AMP

5) Commuting sequence is selected by hall sensor input, and the minimum hall input is 50mV.

6) The gain and limit currents are calculated as shown in the table below.(Gvo=V

AMP

/(SPIN-V

REF

)=1[V/V]).

7) Spindle block adopts 180

commutation methodology which is fully compatible with a conventional BLDC spindle motor. Users

don't need to change or modify their spindle motor.
8) The range of the input voltage is as shown below when Rcs=0.33

, R

EXT1

=0.

Limit current

Input/Output gain[A/V]

Remark

is gain scaler

Torque AMP

REF

SPIN

Commutator

Driver

Rcs

Vcs

AMP

LPF

Clock

Generator

Hall sensor

EXT1

VM1

Inside IC

IOMAX

10K

0.5

Rcs

-----------

10K

EXT1

10K

-------------------------------------------

RCS

--------------

10K

EXT1

10K

-------------------------------------------

Forward

Dead

Reverse

[A]

SPIN-V

REF

1.5

50mV

-50mV

zone-

MSP

/ R

Dead

zone+

Current

Rotation

MUTE2

SPIN

> V

REF

Forward rotation

SPIN

< V

REF

Reverse brake

MUTE2

=L,open

Short brake

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2. Torque Control & Output Current Control Of Sled Motor(2-phase Step Motor)

1) By amplifying the voltage difference between V

REF

and SLIN1(or SLIN2) from Servo IC(or DSP), the Torque AMP produces

the input voltage(V

AMP

) which means input current command.

2) The output current (I

) is converted into the voltage (V

) through the sense resistor (R

) and compared with the V

AMP

3) The clock generator always make the RS latch become set periodically, this enables the output driver's on state, when the V

and the V

AMP

are equal the state becomes off.

4) By the negative feedback loop, the sensed output voltage V

equals to the V

AMP

5) To avoid output upper and lower transistor's short through, a switch trick is needed. Turn on delay time is 1usec, so the phase
delay time,when changing the current direction, is 1usec.
6) The gain and limit currents are calculated as shown in the table below.(Gvo=V

AMP

/[SLIN1(or SLIN2)-V

REF

]=1[V/V]

The range of the torque voltage is as shown below when Rcs=1W, R

EXT1

Torque limit current

Input/Output gain[A/V]

Remark

is gain scaler

Torque AMP

SLIN1

Driver

Rcs

Vcs

VM2

AMP

LPF

Clock

Generator

Drive Logic

Inside IC

OMAX

(or SLIN2)

REF

EXT1

10K

0.5

Rcs

-----------

10K

EXT1

10K

-------------------------------------------

--------------

10K

EXT1

10K

-------------------------------------------

Forward

Dead

Reverse

[A]

SLIN1(or SLIN2)-V

REF

0.5

15mV

-15mV

zone-

MSL

/ R

Dead

zone+

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3. Channel 1~4 Schematic

· The reference voltage(ref) is given externally through pin21.

· The input OP-amp output signal is amplified by (20K/10K) times and then fed to the power amplifier. The gain of power amplifier is

4 so the total max gain of channels 1 through 4 is 8.

4. Mute Inputs

FAN8741 has 2 independent mute pins: Pin #22(MUTE1) and Pin #23(MUTE2). Details are shown below.

Note:

To make the spindle short brake, MUTE2 goes low and the spindle command must not be in deadzone(±50mV). When the spindle

command is within the deadzone, the spindle block enters disable mode even though MUTE2 is low.

MUTE1

MUTE2

SPIN-

DLE

SLED

CH1/2/3

CH4(typ. load-

ing driver)

SPINDLE brake type

Enable

Disable

Reverse brake when

SPIN<VREF

Enable

Disable

Short brake

SPIN

VREF

(note)

Disable

Enable

Disable

Enable

Disable

L
e
v
e
l sh
if
t

20k

10k

ref

power amp

Command

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5. Reverse Rotation Prevention(Spindle)

1) As in the state of the forward rotation, the D-F/F output, Q is HIGH and the motor rotates normally. At this state, if the control
input is changed such that VREF>SPIN, then the motor rotates slowly by the reverse commutation in the driver. When the
motor begins to rotate in the reverse direction, the D-F/F output becomes Low and the OR Gate output becomes Low. This
prevents the motor from continuing to rotate in the reverse direction. This operation principle is shown in the following table
and flow chart.

Rotation

D-F/F

(Q)

Reverse Rotation Preventer

REF

<SPIN

REF

>SPIN

Forward

Reverse

Brake and Stop

Current

Sense

Amp

Gain

Controller

Driver

D-F/F

HW+

HW-

HV+

HV-

SPIN

VREF

Low Active

Forward rotation at VREF< SPIN

Rotating speed is decreased due to reverse torque at VREF>SPIN

At the moment that the motor rotates in reverse, the reverse rotation preventer makes

Motor rotates in reverse for short time due to motor inertia

and appropriate mute combination. (Motor still rotates forward)

the output power stage equal to the short brake which is lower ,and three power transistors are fully turned on.

Power stage remains in short brake scheme until forward rotation command is received.

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6. Hall Sensor Connection

7. PWM frequency

The PWM operation of the spindle and sled channels are controlled by an internal clock generator with a typical frequency of 100KHz.

8. ETC

1) FG and DIR output s are open-collector types.

2) By-pass capacitors are recommended at hall sensor and power supply inputs.

SVcc1

HALL 1

HALL 2

HALL 3

SVcc1

HALL 1

HALL 2

HALL 3

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FAN8741/FAN8742 Rev. 1.0.1

8741

8
742

indl

e mot

and 6-

CH act

uator dri

ver

Typical Application Circuits(FAN8741MTF example)

Component

Reference value

Remark

R1~R7

10k

Gain scaling resistors. Please refer to pages 12,13, and 14.

R_hall1,R_hall2

100

Hall bias resistors

RSL1,RSL2

Rcs at sled driver. (I_limit=0.5A,Gain=0.5A/V@R6,R7 are 10k

)

RSP

0.33

Rcs at spindle driver. (I_limit=1.5A,Gain=1.5A/V@R1 is 10k

)

Bypass electrolytic capacitors(47~100

F) are recommended at power supply inputs.

HALL-U

HALL-V

HALL-W

3-Phase

BLDC Motor

Sled(stepping)

Motor

Focus

actuator

VM2

(for sled, 5~12V)

FAN

8
7
4
1
M

TF/

8
7
42M

(pad

)

DO2

PVCC3

DO3

DO4+

IN4

IN3

VDD

SPIN

PGND5

DO4

DO3+

DIR

CP1

CP2

VCP

DGND

SVCC1

DO1

DO2+

IN1

DO1+

PGND4

PVCC1

IN2

PVCC2

SLIN2

SLIN1

SL2+

RSP2

SL1+

RSP1

PGND1

PGND2

SL1

HV+

HU+

VM1

HW+

PGND3

SL2

MUTE2

REF

MUTE1

RSL2

RSL1

VM2

SGND

SVCC2

VM1

(for spindle,12V)

SVCC2(5~12V)

(SVCC2

PVCC1,2,3)

Tracking

actuator

Tilt actuator

motor

PVCC2(5~12V)

PVCC1(5~12V)

PVCC3(5~12V)

VDD (5V)

SVCC1(5V)

SP or

ntrol

l
e
r

u
l
l
up
R)

u
l
l
u

p

R)

0.1

RSL1

RSL2

RSP

R_hall2

R_hall1

www.fairchildsemi.com

FAN8741/FAN8742 Rev. 1.0.1

8741

8
742

indl

e mot

and 6-

CH act

uator dri

ver

Typical Application Circuits(FAN8741G example)

Component

Reference value

Remark

R1~R7

10k

Gain scaling resistors. Please refer to 12,13,14 pages.

R_hall1,R_hall2

100

Hall bias resistors

RSL1,RSL2

Rcs at sled driver. (I_limit=0.5A,Gain=0.5A/V@R6,R7 are 10k

)

RSP

0.33

Rcs at spindle driver. (I_limit=1.5A,Gain=1.5A/V@R1 is 10k

)

Bypass electrolytic capacitors(47~100

F) are recommended at power supply inputs.

HALL-U

HALL-V

HALL-W

3-Phase

BLDC Motor

Sled(stepping)

Motor

Focus

actuator

VM2

(for sled, 5~12V)

FA
N8741

FA
N8742G

DO2

PVCC3

DO3

DO4+

IN4

IN3

VDD

SPIN

PGND5

DO4

DO3+

DIR

CP1

CP2

VCP

DGND

SVCC1

DO1

DO2+

IN1

DO1+

PGND4

PVCC1

IN2

PVCC2

SLIN2

SLIN1

SL2+

RSP2

SL1+

RSP1

PGND1

PGND2

SL1

HV+

HU+

VM1

HW+

PGND3

SL2

MUTE2

REF

MUTE1

RSL2

RSL1

VM2

SGND

SVCC2

VM1

(for spindle,12V)

SVCC2(5~12V)

(SVCC2

PVCC1,2,3)

Tracking

actuator

Tilt actuator

motor

PVCC2(5~12V)

PVCC1(5~12V)

PVCC3(5~12V)

VDD (5V)

SVCC1(5V)

DS
P or

con
t
r
o
l
l
er

10k

(
f
ul

l
up

10k

(
f
ul

l
up R

)

0.1

RSL1

RSL2

RSP

R_hall2

R_hall1

0.1

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