FDC6506P
FDC6506P Rev. C
FDC6506P
Dual P-Channel Logic Level PowerTrench
TM
MOSFET
February 1999
1999 Fairchild Semiconductor Corporation
Absolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol
Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
-30
V
V
GSS
Gate-Source Voltage
20
V
I
D
Drain Current
- Continuous
(Note 1a)
-1.8
A
- Pulsed
-10
P
D
Power Dissipation for Single Operation
(Note 1a)
0.96
W
(Note 1b)
0.9
(Note 1c)
0.7
T
J
, T
stg
Operating and Storage Junction Temperature Range
-55 to +150
C
Thermal Characteristics
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
130
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
60
C/W
Package Outlines and Ordering Information
Device Marking
Device
Reel Size
Tape Width
Quantity
.
506
FDC6506P
7''
8mm
3000 units
5
6
4
2
3
1
General Description
These P-Channel logic level MOSFETs are produced using
Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize
on-state resistance and yet maintain low gate charge for
superior switching performance.
These devices have been designed to offer exceptional
power dissipation in a very small footprint for applications
where the bigger more expensive SO-8 and TSSOP-8
packages are impractical.
Applications
Load switch
Battery protection
Power management
Features
-1.8 A, -30 V. R
DS(on)
= 0.170
@ V
GS
= -10 V
R
DS(on)
= 0.280
@ V
GS
= -4.5 V
Low gate charge (2.3nC typical).
Fast switching speed.
High performance trench technology for extremely
low R
DS(ON)
.
SuperSOT
TM
-6 package: small footprint (72% smaller
than standard SO-8); low profile (1mm thick).
D1
S2
G1
D2
S1
G2
SuperSOT -6
TM
FDC6506P
FDC6506P Rev. C
a) 130
C/W when
mounted on a 0.125 in
2
pad of 2 oz. copper.
b) 140
C/W when
mounted on a 0.005 in
2
pad of 2 oz. copper.
c) 180
C/W when
mounted on a 0.0015 in
2
pad of 2 oz. copper.
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface
of the drain pins. R
JC
is guaranteed by design while R
JA
is determined by the user's board design.Both devices are assumed to be operating and
sharing the dissipated heat energy equally.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width
300
s, Duty Cycle
2.0%
Electrical Characteristics
T
A
= 25C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= -250
A
-30
V
BV
DSS
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= -250
A, Referenced to 25
C
-20
mV/
C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -24 V, V
GS
= 0 V
-1
A
I
GSSF
Gate-Body Leakage Current, Forward
V
GS
= 20 V, V
DS
= 0 V
100
nA
I
GSSR
Gate-Body Leakage Current, Reverse
V
GS
= -20 V, V
DS
= 0 V
-100
nA
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250
A
-1
-1.8
-3
V
V
GS(th)
T
J
Gate Threshold Voltage
Temperature Coefficient
I
D
= -250
A, Referenced to 25
C
4
mV/
C
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= -10 V, I
D
= -1.8 A
V
GS
= -10 V, I
D
= -1.8 A @125
C
V
GS
= -4.5 V, I
D
= -1.4 A
0.14
0.20
0.22
0.17
0.27
0.28
I
D(on)
On-State Drain Current
V
GS
= -10 V, V
DS
= - 5 V
-10
A
g
FS
Forward Transconductance
V
DS
= -5 V, I
D
= -1.8 A
3
S
Dynamic Characteristics
C
iss
Input Capacitance
190
pF
C
oss
Output Capacitance
70
pF
C
rss
Reverse Transfer Capacitance
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
30
pF
Switching Characteristics
(Note 2)
t
d(on)
Turn-On Delay Time
7
14
ns
t
r
Turn-On Rise Time
8
16
ns
t
d(off)
Turn-Off Delay Time
14
25
ns
t
f
Turn-Off Fall Time
V
DD
= -15 V, I
D
= -1 A,
V
GS
= -4.5 V, R
GEN
= 6
2
6
ns
Q
g
Total Gate Charge
2.3
3.5
nC
Q
gs
Gate-Source Charge
1
nC
Q
gd
Gate-Drain Charge
V
DS
= -5 V, I
D
= -1.8 A,
V
GS
= -10 V
0.8
nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current
-0.8
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.8 A
(Note 2)
-0.8
-1.2
V
FDC6506P
FDC6506P Rev. C
Typical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation
with Gate-to-Source Voltage.
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-50
-25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (
o
C)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
=-1.8A
V
GS
=-10V
0
2
4
6
8
10
0
1
2
3
4
5
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
-I
D
, DRAIN CURRENT (A)
V
GS
=-10V
-7.0V
-5.5V
-4.5V
-4.0V
-3.5V
-3.0V
0.5
1
1.5
2
2.5
0
2
4
6
8
10
-I
D
, DRAIN CURRENT (A)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
=-4.0V
-4.5V
-5.0V
-6.0V
-7.0V
-10V
0
1
2
3
4
1
2
3
4
5
-V
GS
, GATE TO SOURCE VOLTAGE (V)
-I
D
, DRAIN CURRENT (A)
V
DS
=-5V
T
J
=-55
o
C
25
o
C
125
o
0.001
0.01
0.1
1
10
0
0.3
0.6
0.9
1.2
1.5
-V
SD
, BODY DIODE VOLTAGE (V)
-I
S
, REVERSE DRAIN C
URRENT
(
A
)
V
GS
=0
T
J
=125
o
C
25
o
C
-55
o
C
0.1
0.2
0.3
0.4
0.5
2
3
4
5
6
7
8
9
10
-V
GS
, GATE TO SOURCE VOLTAGE (V)
R
DS
(
O
N)
,
O
N
-
R
ESI
ST
A
N
C
E
(
O
H
M
)
T
J
=125
o
C
25
o
C
I
D
=-1.0A
FDC6506P
FDC6506P Rev. C
Typical Characteristics
(continued)
Figure 7. Gate-Charge Characteristics.
Figure 8. Capacitance Characteristics.
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient themal response will change depending on the circuit board design.
0.0001
0.001
0.01
0.1
1
10
100
300
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
T
R
A
N
SI
EN
T
T
H
E
R
M
A
L
RE
SI
ST
ANCE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
r(
t
)
,
NO
RM
ALI
ZE
D EF
FE
C
T
I
V
E
Duty Cycle, D = t / t
1
2
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
R (t) = r(t) * R
R =180C/W
JA
JA
JA
0.01
0.1
1
10
100
300
0
1
2
3
4
5
SINGLE PULSE TIME (SEC)
PO
W
E
R
(
W
)
SINGLE PULSE
R =180C/W
T = 25C
JA
A
0.1
0.2
0.5
1
2
5
10
20
50
0.01
0.03
0.1
0.3
1
3
10
30
-V , DRAIN-SOURCE VOLTAGE (V)
-
I
,
DR
AI
N
CUR
RE
N
T
(
A
)
RDS(
ON)
LI
MI
T
D
DS
V = -10V
SINGLE PULSE
R = 180C/W
T = 25C
JA
GS
A
DC
1s
100ms
10ms
1ms
100us
0
2
4
6
8
10
0
1
2
3
4
Q
g
, GATE CHARGE (nC)
-V
GS
, GA
T
E
-
S
OU
R
C
E
VOL
T
A
G
E (
V
)
I
D
= -1.8A
V
DS
=-5.0V
-10V
-15V
0
60
120
180
240
300
0
6
12
18
24
30
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
CA
P
A
C
I
TAN
C
E
(pF)
C
iss
C
oss
C
rss
f=1MHz
V
GS
=0V
1998 Fairchild Semiconductor Corporation
SSOT-6 Unit Orientation
Conductive Embossed
Carrier Tape
F63TNR
Label
Customize Label
Antistatic Cover Tape
SSOT-6 Packaging
Configuration: Figure 1.0
Components
Leader Tape
390mm minimum
Trailer Tape
160mm minimum
SSOT-6 Tape Leader
Trailer
Configuration: Figure 2.0
Cover Tape
Carrier
Pin 1
Tape
Note/Comments
Packaging Option
SSOT-6 Packaging Information
Standard
(no flow code)
D87Z
Packaging type
Reel Size
TNR
7" Dia
TNR
13"
Qty per Reel/Tube/Bag
3,000
10,000
Box Dimension (mm)
184x187x47
343x343x64
Max qty per Box
9,000
20,000
Weight per unit (gm)
0.0158
0.0158
Weight per Reel (kg)
0.1440
0.4700
184mm x 184mm x 47mm
Pizza Box for Standard Option
F63TNR
Label
F63TNR Label
F63TNR Label sample
343mm x 342mm x 64mm
Intermediate box for D87Z Option
631
631
631
631
LOT: CBVK741B019
FSID: FDC633N
D/C1: D9842
QTY1:
SPEC REV: QARV:
SPEC:
QTY: 3000
D/C2:
QTY2:
CPN:
(F63TNR)2
F63TNR
Label
SuperSOT
TM
-6 Tape and Reel Data and Package Dimensions
December 1998, Rev. B
P1
A0
D1
P0
F
W
E1
D0
E2
B0
Tc
Wc
K0
T
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
8mm
7" Dia
7.00
177.8
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 0.429
7.9 10.9
8mm
13" Dia
13.00
330
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
4.00
100
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 0.429
7.9 10.9
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Option
Dim A
Max
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim D
min
Dim C
B Min
DETAIL AA
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum component rotation
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
Typical
component
cavity
center line
20 deg maximum
Typical
component
center line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or Front Sectional View)
Component Rotation
User Direction of Feed
SSOT-6 Embossed Carrier Tape
Configuration: Figure 3.0
SSOT-6 Reel Configuration: Figure 4.0
Dimensions are in millimeter
Pkg type
A0
B0
W
D0
D1
E1
E2
F
P1
P0
K0
T
Wc
Tc
SSOT-6
(8mm)
3.23
+/-0.10
3.18
+/-0.10
8.0
+/-0.3
1.55
+/-0.05
1.00
+/-0.125
1.75
+/-0.10
6.25
min
3.50
+/-0.05
4.0
+/-0.1
4.0
+/-0.1
1.37
+/-0.10
0.255
+/-0.150
5.2
+/-0.3
0.06
+/-0.02
SuperSOT
TM
-6 Tape and Reel Data and Package Dimensions, continued
December 1998, Rev. B
1998 Fairchild Semiconductor Corporation
SuperSOT
TM
-6 (FS PKG Code 31, 33)
1 : 1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0158
SuperSOT
TM
-6 Tape and Reel Data and Package Dimensions, continued
September 1998, Rev. A
TRADEMARKS
ACExTM
CoolFETTM
CROSSVOLTTM
E
2
CMOS
TM
FACTTM
FACT Quiet SeriesTM
FAST
FASTrTM
GTOTM
HiSeCTM
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
ISOPLANARTM
MICROWIRETM
POPTM
PowerTrenchTM
QSTM
Quiet SeriesTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
TinyLogicTM
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
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