February 2001
2001 Fairchild Semiconductor Corporation
FDD5614P Rev C(W)
FDD5614P
60V P-Channel PowerTrench
MOSFET
General Description
This 60V P-Channel MOSFET uses Fairchild's high
voltage PowerTrench process. It has been optimized
for power management applications.
Applications
DC/DC converter
Power management
Load switch
Features
15 A, 60 V. R
DS(ON)
= 100 m
@ V
GS
= 10 V
R
DS(ON)
= 130 m
@ V
GS
= 4.5 V
Fast switching speed
High performance trench technology for extremely
low R
DS(ON)
High power and current handling capability
G
S
D
TO-252
S
G
D
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol
Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
60
V
V
GSS
Gate-Source Voltage
20
V
I
D
Drain Current Continuous
(Note 3)
15
A
Pulsed
(Note 1a)
45
Power Dissipation for Single Operation
(Note 1)
42
(Note 1a)
3.8
P
D
(Note 1b)
1.6
W
T
J
, T
STG
Operating and Storage Junction Temperature Range
55 to +175
C
Thermal Characteristics
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
3.5
C/W
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
40
C/W
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1b)
96
C/W
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
FDD5614P
FDD5614P
13''
12mm
2500 units
F
DD56
14P
FDD5614P Rev C(W)
Electrical Characteristics
T
A
= 25C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Drain-Source Avalanche Ratings
(Note 1)
W
DSS
Single Pulse Drain-Source
Avalanche Energy
V
DD
= 30 V,
I
D
= 4.5 A
90
mJ
I
AR
Maximum Drain-Source Avalanche
Current
4.5
A
Off Characteristics
BV
DSS
DrainSource Breakdown Voltage
V
GS
= 0 V, I
D
= 250
A
60
V
BV
DSS
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250
A, Referenced to 25
C
49
mV/
C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 48 V,
V
GS
= 0 V
1
A
I
GSSF
GateBody Leakage, Forward
V
GS
= 20V,
V
DS
= 0 V
100
nA
I
GSSR
GateBody Leakage, Reverse
V
GS
= 20 V,
V
DS
= 0 V
100
nA
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250
A
1
1.6
3
V
V
GS(th)
T
J
Gate Threshold Voltage
Temperature Coefficient
I
D
= 250
A, Referenced to 25
C
4
mV/
C
R
DS(on)
Static DrainSource
OnResistance
V
GS
= 10 V,
I
D
= 4.5 A
V
GS
= 4.5 V,
I
D
= 3.9 A
V
GS
= 10 V,I
D
= 4.5 A,T
J
=125
C
76
99
137
100
130
185
m
I
D(on)
OnState Drain Current
V
GS
= 10 V,
V
DS
= 5 V
20
A
g
FS
Forward Transconductance
V
DS
= 5 V,
I
D
= 3 A
8
S
Dynamic Characteristics
C
iss
Input Capacitance
759
pF
C
oss
Output Capacitance
90
pF
C
rss
Reverse Transfer Capacitance
V
DS
= 30 V,
V
GS
= 0 V,
f = 1.0 MHz
39
pF
Switching Characteristics
(Note 2)
t
d(on)
TurnOn Delay Time
7
14
ns
t
r
TurnOn Rise Time
10
20
ns
t
d(off)
TurnOff Delay Time
19
34
ns
t
f
TurnOff Fall Time
V
DD
= 30 V,
I
D
= 1 A,
V
GS
= 10 V,
R
GEN
= 6
12
22
ns
Q
g
Total Gate Charge
15
24
nC
Q
gs
GateSource Charge
2.5
nC
Q
gd
GateDrain Charge
V
DS
= 30V,
I
D
= 4.5 A,
V
GS
= 10 V
3.0
nC
DrainSource Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous DrainSource Diode Forward Current
3.2
A
V
SD
DrainSource Diode Forward
Voltage
V
GS
= 0 V,
I
S
= 3.2 A
(Note 2)
0.8
1.2
V
F
DD56
14P
FDD5614P Rev C(W)
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
JC
is guaranteed by design while R
CA
is determined by the user's board design.
a) R
JA
= 40C/W when mounted on a
1in
2
pad of 2 oz copper
b) R
JA
= 96C/W when mounted
on a minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300
s, Duty Cycle < 2.0%
3. Maximum current is calculated as:
where P
D
is maximum power dissipation at T
C
= 25C and R
DS(on)
is at T
J(max)
and V
GS
= 10V. Package current limitation is 21A
)
ON
(
DS
D
R
P
F
DD56
14P
FDD5614P Rev C(W)
Typical Characteristics
0
3
6
9
12
15
0
1
2
3
4
5
-V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRE
NT (
A
)
-3.0V
-2.5V
-4.0V
-4.5V
V
GS
= -10V
-3.5V
-6.0V
0.8
1
1.2
1.4
1.6
1.8
0
2
4
6
8
10
-I
D
, DRAIN CURRENT (A)
R
DS
(
O
N)
, NO
RMALIZE
D
DRAIN-
S
O
URCE
O
N
-
R
E
S
I
S
T
ANCE
V
GS
= -3.5V
-4.5V
-5.0V
-4.0V
-10V
-6.0V
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-50
-25
0
25
50
75
100
125
150
175
T
J
, JUNCTION TEMPERATURE (
o
C)
R
DS
(
O
N)
, NO
RMALIZE
D
DRAIN-
S
O
URCE
O
N
-
R
E
S
I
S
T
ANC
E
I
D
= -4.5A
V
GS
= -10V
0
0.1
0.2
0.3
0.4
2
4
6
8
10
-V
GS
, GATE TO SOURCE VOLTAGE (V)
R
DS
(
O
N)
, O
N
-
R
E
S
I
S
T
ANCE
(
O
HM)
I
D
= -2.3 A
T
A
= 125
o
C
T
A
= 25
o
C
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
3
6
9
12
15
1
2
3
4
5
-V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRE
NT (
A
)
T
A
= -55
o
C
125
o
C
V
DS
= -5V
25
o
C
0.001
0.01
0.1
1
10
100
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
I
S
,
R
EVER
SE
DRAIN CURRE
NT (
A
)
T
A
= 125
o
C
25
o
C
-55
o
C
V
GS
= 0V
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
F
DD56
14P
FDD5614P Rev C(W)
Typical Characteristics
0
2
4
6
8
10
0
4
8
12
16
Q
g
, GATE CHARGE (nC)
V
GS
, G
A
TE
-
S
O
URCE
V
O
LTAG
E
(
V
)
I
D
= -4.5A
V
DS
= -40V
-20V
-30V
0
200
400
600
800
1000
0
10
20
30
40
50
60
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
CAP
ACITANCE
(
pF)
C
ISS
C
RSS
C
OSS
f = 1MHz
V
GS
= 0 V
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.1
1
10
100
-V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRE
NT (
A
)
DC
10s
1s
100ms
100
s
R
DS(ON)
LIMIT
V
GS
= -10V
SINGLE PULSE
R
JA
= 96
o
C/W
T
A
= 25
o
C
10ms
1ms
0
10
20
30
40
0.1
1
10
100
1000
t
1
, TIME (sec)
P
(
pk
)
,
P
E
AK TRANS
IE
NT P
O
WE
R (
W
)
SINGLE PULSE
R
JA
= 96C/W
T
A
= 25C
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
R
JA
(t) = r(t) + R
JA
R
JA
= 96C/W
T
J
- T
A
= P * R
JA
(t)
Duty Cycle, D = t
1
/ t
2
P(pk
)
t
1
t
2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
F
DD56
14P
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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