2006 Fairchild Semiconductor Corporation
1
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FDD6N50/FDU6N50 REV. A
F
DD6N50/FDU6N50 50
0V N-Channe
l MOSFET
January 2006
UniFET
TM
FDD6N50
/FDU6N50
500V N-Channel MOSFET
Features
6A, 500V, R
DS(on)
= 0.9
@V
GS
= 10 V
Low gate charge ( typical 12.8 nC)
Low C
rss
( typical 9 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies and active power factor
correction.
I-PAK
FDU Series
D-PAK
FDD Series
G
S
D
G
S
D
D
G
S
Absolute Maximum Ratings
Symbol
Parameter
FDD6N50/FDU6N50
Unit
V
DSS
Drain-Source Voltage
500
V
I
D
Drain Current
- Continuous (T
C
= 25
C)
- Continuous (T
C
= 100
C)
6
3.8
A
A
I
DM
Drain Current
- Pulsed
(Note 1)
24
A
V
GSS
Gate-Source voltage
30
V
E
AS
Single Pulsed Avalanche Energy
(Note 2)
270
mJ
I
AR
Avalanche Current
(Note 1)
6
A
E
AR
Repetitive Avalanche Energy
(Note 1)
8.9
mJ
dv/dt
Peak Diode Recovery dv/dt
(Note 3)
4.5
V/ns
P
D
Power Dissipation
(T
C
= 25
C)
- Derate above 25
C
89
0.71
W
W/
C
T
J,
T
STG
Operating and Storage Temperature Range
-55 to +150
C
T
L
Maximum Lead Temperature for Soldering Purpose,
1/8" from Case for 5 Seconds
300
C
Thermal Characteristics
Symbol
Parameter
Min.
Max.
Unit
R
JC
Thermal Resistance, Junction-to-Case
--
1.4
C/W
R
JA
Thermal Resistance, Junction-to-Ambient
--
83
C/W
2
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FDD6N50/FDU6N50 REV. A
F
DD6N50/FDU6N50 50
0V N-Channe
l MOSFET
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDD6N50
FDD6N50TM
D-PAK
380mm
16mm
2500
FDD6N50
FDD6N50TF
D-PAK
380mm
16mm
2000
FDU6N50
FDU6N50TU
I-PAK
-
-
70
Electrical Characteristics
T
C
= 25C unless otherwise noted
Symbol
Parameter
Conditions
Min.
Typ.
Max Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0V, I
D
= 250
A
500
--
--
V
BV
DSS
/
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250
A, Referenced to 25C
--
0.5
--
V/
C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 500V, V
GS
= 0V
V
DS
= 400V, T
C
= 125
C
--
--
--
--
1
10
A
A
I
GSSF
Gate-Body Leakage Current, Forward
V
GS
= 30V, V
DS
= 0V
--
--
100
nA
I
GSSR
Gate-Body Leakage Current, Reverse
V
GS
= -30V, V
DS
= 0V
--
--
-100
nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250
A
3.0
--
5.0
V
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= 10V, I
D
= 3A
--
0.76
0.9
g
FS
Forward Transconductance
V
DS
= 40V, I
D
= 3A
(Note 4)
--
2.5
--
S
Dynamic Characteristics
C
iss
Input Capacitance
V
DS
= 25V, V
GS
= 0V,
f = 1.0MHz
--
720
940
pF
C
oss
Output Capacitance
--
95
190
pF
C
rss
Reverse Transfer Capacitance
--
9
13.5
pF
Switching Characteristics
t
d(on)
Turn-On Delay Time
V
DD
= 250V, I
D
= 6A
R
G
= 25
(Note 4, 5)
--
6
20
ns
t
r
Turn-On Rise Time
--
55
120
ns
t
d(off)
Turn-Off Delay Time
--
25
60
ns
t
f
Turn-Off Fall Time
--
35
80
ns
Q
g
Total Gate Charge
V
DS
= 400V, I
D
= 6A
V
GS
= 10V
(Note 4, 5)
--
12.8
16.6
nC
Q
gs
Gate-Source Charge
--
3.7
--
nC
Q
gd
Gate-Drain Charge
--
5.8
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current
--
--
6
A
I
SM
Maximum Pulsed Drain-Source Diode Forward Current
--
--
24
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0V, I
S
= 6A
--
--
1.4
V
t
rr
Reverse Recovery Time
V
GS
= 0V, I
S
= 6A
dI
F
/dt =100A/
s
(Note 4)
--
275
--
ns
Q
rr
Reverse Recovery Charge
--
1.7
--
C
NOTES:
1. Repetitive Rating: Pulse width limited by maximum junction temperature
2. I
AS
= 6A, V
DD
= 50V, L=13.5mH, R
G
= 25
, Starting T
J
= 25
C
3. I
SD
6A, di/dt 200A/s, V
DD
BV
DSS
, Starting T
J
= 25
C
4. Pulse Test: Pulse width
300s, Duty Cycle 2%
5. Essentially Independent of Operating Temperature Typical Characteristics
3
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FDD6N50/FDU6N50 REV. A
F
DD6N50/FDU6N50 50
0V N-Channe
l MOSFET
Typical Performance Characteristics
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
Figure 3. On-Resistance Variation vs.
Figure 4. Body Diode Forward Voltage
Drain Current and Gate Voltage
Variation vs. Source Current
and Temperature
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
2
4
6
8
10
10
-2
10
-1
10
0
10
1
Note
1. V
DS
= 40V
2. 250s Pulse Test
-55
150
25
I
D
,
Dr
ain
Cu
r
r
ent
[
A
]
V
GS
, Gate-Source Voltage [V]
0
10
20
30
40
50
0
5
10
15
20
V
GS
Top : 10.0 V
8.0V
7.5 V
7.0 V
6.5 V
6.0 V
5.5 V
Bottom : 5.0 V
Notes :
1. 250s Pulse Test
2. T
C
= 25
I
D
, D
r
ain
Cu
rrent [A]
V
DS
, Drain-Source Voltage [V]
0
5
10
15
20
0.0
0.5
1.0
1.5
2.0
2.5
V
GS
= 20V
V
GS
= 10V
Note : T
J
= 25
R
DS(O
N
)
[
]
,
D
r
a
in-
S
our
ce O
n
-
R
esist
a
nce
I
D
, Drain Current [A]
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
10
-1
10
0
10
1
25
150
Notes :
1. V
GS
= 0V
2. 250s Pulse Test
I
DR
,
Re
verse
Dr
ain Cu
rr
ent
[
A
]
V
SD
, Source-Drain Voltage [V]
10
0
10
1
10
100
1000
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
Notes :
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
C
oss
C
iss
Cap
a
c
i
t
a
nc
e [
p
F]
V
DS
, Drain-Source Voltage [V]
0
5
10
15
0
2
4
6
8
10
12
V
DS
= 250V
V
DS
= 100V
V
DS
= 400V
Note : I
D
= 6A
V
GS
, Ga
te
-So
u
rce Vo
l
t
a
g
e
[V
]
Q
G
, Total Gate Charge [nC]
4
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FDD6N50/FDU6N50 REV. A
F
DD6N50/FDU6N50 50
0V N-Channe
l MOSFET
Typical Performance Characteristics
(Continued)
Figure 7. Breakdown Voltage Variation
Figure 8. On-Resistance Variation
vs. Temperature
vs. Temperature
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 11. Transient Thermal Response Curve
-100
-50
0
50
100
150
200
0.8
0.9
1.0
1.1
1.2
Notes :
1. V
GS
= 0 V
2. I
D
= 250
A
BV
DSS
, (N
orm
a
l
i
ze
d)
D
r
a
i
n-Source Br
e
a
kdown V
o
l
t
a
g
e
T
J
, Junction Temperature [
o
C]
-100
-50
0
50
100
150
200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes :
1. V
GS
= 10 V
2. I
D
= 3 A
R
DS
(
O
N)
,
(
N
or
ma
liz
e
d
)
D
r
a
i
n-
S
o
u
r
ce
O
n
-
R
esi
s
t
a
nce
T
J
, Junction Temperature [
o
C]
25
50
75
100
125
150
0
2
4
6
8
I
D
,
D
r
ain
Cur
r
en
t [
A
]
T
C
, Case Temperature [ ]
10
0
10
1
10
2
10
3
10
-2
10
-1
10
0
10
1
10
2
10 us
Operation in This Area
is Limited by R
DS(on)
DC
10 ms
1 ms
100 us
Notes :
1. T
C
= 25
o
C
2. T
J
= 150
o
C
3. Single Pulse
I
D
, Drain Current
[
A
]
V
DS
, Drain-Source Voltage [V]
1 0
-5
1 0
-4
1 0
-3
1 0
-2
10
-1
1 0
0
1 0
1
1 0
-2
1 0
-1
1 0
0
N o te s :
1 . Z
JC
(t) = 1 .4 /W M a x.
2 . D u ty F a cto r, D = t
1
/t
2
3 . T
JM
- T
C
= P
D M
* Z
JC
(t)
single pulse
D =0.5
0.02
0.2
0.05
0.1
0.01
Z
JC
(t
),
Th
e
r
m
a
l
R
e
s
p
o
n
s
e
t
1
, S q u a re W a ve P u lse D u ra tio n [se c]
t
1
P
DM
t
2
5
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FDD6N50/FDU6N50 REV. A
F
DD6N50/FDU6N50 50
0V N-Channe
l MOSFET
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
6
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FDD6N50/FDU6N50 REV. A
F
DD6N50/FDU6N50 50
0V N-Channe
l MOSFET
Peak Diode Recovery dv/dt Test Circuit & Waveforms
7
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FDD6N50/FDU6N50 REV. A
F
DD6N50/FDU6N50 50
0V N-Channe
l MOSFET
Mechanical Dimensions
D-PAK
Dimensions in Millimeters
8
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FDD6N50/FDU6N50 REV. A
F
DD6N50/FDU6N50 50
0V N-Channe
l MOSFET
Mechanical Dimensions
(Continued)
I-PAK
Dimensions in Millimeters
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
ISOPLANARTM
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MICROCOUPLERTM
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I
2
CTM
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Rev. I18
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CROSSVOLTTM
DOMETM
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E
2
CMOSTM
EnSignaTM
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QFET
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QT OptoelectronicsTM
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SILENT SWITCHER
SMART STARTTM
SPMTM
StealthTM
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SuperSOTTM-3
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SuperSOTTM-8
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Across the board. Around the world.TM
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