2005 Fairchild Semiconductor Corporation
FDD8878 / FDU8878 Rev. A3
January 2005
www.fairchildsemi.com
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1
FDD8878 / FDU8878
N-Channel PowerTrench
MOSFET
30V, 40A, 15m
Features
r
DS(ON)
= 15m
, V
GS
= 10V, I
D
= 35A
r
DS(ON)
= 18.5m
, V
GS
= 4.5V, I
D
= 35A
High performance trench technology for extremely low
r
DS(ON)
Low gate charge
High power and current handling capability
Applications
DC/DC converters
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
r
DS(ON)
and fast switching speed.
D
G
S
G D S
I-PAK
(TO-251AA)
G
S
D
TO-252
D-PAK
(TO-252)
2005 Fairchild Semiconductor Corporation
FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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2
Absolute Maximum Ratings
T
C
= 25C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Electrical Characteristics
T
C
= 25C unless otherwise noted
Off Characteristics
On Characteristics
Symbol
Parameter
Ratings
Units
V
DSS
Drain to Source Voltage
30
V
V
GS
Gate to Source Voltage
20
V
I
D
Drain Current
40
A
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Note 1)
Continuous (T
C
= 25
o
C, V
GS
= 4.5V) (Note 1)
36
A
Continuous (T
amb
= 25
o
C, V
GS
= 10V, with R
JA
= 52
o
C/W)
11
A
Pulsed
Figure 4
A
E
AS
Single Pulse Avalanche Energy (Note 2)
25
mJ
P
D
Power dissipation
40
W
Derate above 25
o
C
0.27
W/
o
C
T
J
, T
STG
Operating and Storage Temperature
-55 to 175
o
C
R
JC
Thermal Resistance Junction to Case TO-252, TO-251
3.75
o
C/W
R
JA
Thermal Resistance Junction to Ambient TO-252, TO-251
100
o
C/W
R
JA
Thermal Resistance Junction to Ambient TO-252, 1in
2
copper pad area
52
o
C/W
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDD8878
FDD8878
TO-252AA
13"
12mm
2500 units
FDU8878
FDU8878
TO-251AA
Tube
N/A
75 units
FDD8878
FDD8878_NL (Note 3)
TO-252AA
13"
12mm
2500 units
FDU8878
FDU8878_NL (Note 3)
TO-251AA
Tube
N/A
75 units
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
B
VDSS
Drain to Source Breakdown Voltage
I
D
= 250
A, V
GS
= 0V
30
-
-
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24V
-
-
1
A
V
GS
= 0V
T
C
= 150
o
C
-
-
250
I
GSS
Gate to Source Leakage Current
V
GS
=
20V
-
-
100
nA
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
A
1.2
-
2.5
V
r
DS(ON)
Drain to Source On Resistance
I
D
= 35A, V
GS
= 10V
-
0.011
0.015
I
D
= 35A, V
GS
= 4.5V
-
0.014
0.0185
I
D
= 35A, V
GS
= 10V,
T
J
= 175
o
C
-
0.018
0.024
2005 Fairchild Semiconductor Corporation
FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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3
Dynamic Characteristics
Switching Characteristics
(V
GS
= 10V)
Drain-Source Diode Characteristics
Notes:
1: Package current limitation is 35A.
2: Starting T
J
= 25C, L = 65uH, I
AS
= 28A, V
DD
= 27V, V
GS
= 10V.
3: FDD8878_NL / FDU8878_NL is lead free product.
FDD8878_NL / FDU8878_NL marking will appear on the reel label.
C
ISS
Input Capacitance
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
-
880
-
pF
C
OSS
Output Capacitance
-
195
-
pF
C
RSS
Reverse Transfer Capacitance
-
110
-
pF
R
G
Gate Resistance
V
GS
= 0.5V, f = 1MHz
-
3.1
-
Q
g(TOT)
Total Gate Charge at 10V
V
GS
= 0V to 10V
V
DD
= 15V
I
D
= 35A
I
g
= 1.0mA
-
19
26
nC
Q
g(5)
Total Gate Charge at 5V
V
GS
= 0V to 5V
-
10
14
nC
Q
g(TH)
Threshold Gate Charge
V
GS
= 0V to 1V
-
0.9
1.3
nC
Q
gs
Gate to Source Gate Charge
-
2.6
-
nC
Q
gs2
Gate Charge Threshold to Plateau
-
1.7
-
nC
Q
gd
Gate to Drain "Miller" Charge
-
4.5
-
nC
t
ON
Turn-On Time
V
DD
= 15V, I
D
= 35A
V
GS
= 4.5V, R
GS
= 16
-
-
129
ns
t
d(ON)
Turn-On Delay Time
-
7
-
ns
t
r
Rise Time
-
79
-
ns
t
d(OFF)
Turn-Off Delay Time
-
38
-
ns
t
f
Fall Time
-
27
-
ns
t
OFF
Turn-Off Time
-
-
97
ns
V
SD
Source to Drain Diode Voltage
I
SD
= 35A
-
-
1.25
V
I
SD
= 3.2A
-
-
1.0
V
t
rr
Reverse Recovery Time
I
SD
= 35A, dI
SD
/dt = 100A/
s
-
-
23
ns
Q
RR
Reverse Recovered Charge
I
SD
= 35A, dI
SD
/dt = 100A/
s
-
-
9
nC
2005 Fairchild Semiconductor Corporation
FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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4
Typical Characteristics
T
C
= 25C unless otherwise noted
Figure 1. Normalized Power Dissipation vs Case
Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
T
C
, CASE TEMPERATURE (
o
C)
PO
WE
R
D
I
SSI
P
A
T
I
O
N
M
U
L
T
I
P
L
I
ER
0
0
25
50
75
100
175
0.2
0.4
0.6
0.8
1.0
1.2
125
150
0
10
20
30
40
50
25
50
75
100
125
150
175
I
D
, DRAIN CURRE
NT
(
A
)
T
C
, CASE TEMPERATURE (
o
C)
CURRENT LIMITED
BY PACKAGE
V
GS
= 4.5V
V
GS
= 10V
0.1
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.01
2
t, RECTANGULAR PULSE DURATION (s)
Z
JC
, NO
RM
AL
IZ
E
D
T
H
E
R
M
A
L
IM
P
E
D
ANCE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
100
30
500
I
DM
, P
E
AK CURRE
NT
(
A
)
t, PULSE WIDTH (s)
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
GS
= 4.5V
V
GS
= 10V
2005 Fairchild Semiconductor Corporation
FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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5
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
Typical Characteristics
T
C
= 25C unless otherwise noted
0.1
1
10
100
1000
1
10
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRE
NT
(
A
)
T
J
= MAX RATED
T
C
= 25
o
C
SINGLE PULSE
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
10
s
1ms
DC
100
s
10ms
1
10
100
0.01
0.1
1
500
10
I
AS
, A
V
AL
ANCHE
CUR
RE
NT
(
A
)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0
20
40
60
80
1.5
2.0
2.5
3.0
3.5
4.0
I
D
, DRAIN CURRE
NT
(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= 25
o
C
T
J
= -55
o
C
0
20
40
60
80
0
0.25
0.5
0.75
1.0
1.25
1.5
I
D
, DRAIN CURRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
V
GS
= 10V
V
GS
= 4V
V
GS
= 3V
V
GS
= 5V
10
15
20
25
30
2
4
6
8
10
I
D
= 1A
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 35A
r
DS(
O
N)
, DRAIN T
O
S
O
UR
CE
O
N
RE
S
I
S
T
ANCE
(
m
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-80
-40
0
40
80
120
160
200
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
T
J
, JUNCTION TEMPERATURE (
o
C)
O
N
RE
S
I
S
T
ANCE
V
GS
= 10V, I
D
= 35A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
2005 Fairchild Semiconductor Corporation
FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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6
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Current
Typical Characteristics
T
C
= 25C unless otherwise noted
0.4
0.6
0.8
1.0
1.2
-80
-40
0
40
80
120
160
200
V
GS
= V
DS
, I
D
= 250
A
NO
RM
AL
IZ
E
D
G
A
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
T
H
R
ESH
O
L
D
V
O
L
T
A
G
E
0.90
0.95
1.00
1.05
1.10
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
I
D
= 250
A
BRE
AKDO
W
N
V
O
L
T
A
G
E
100
1000
0.1
1
10
50
2000
30
C, CAP
A
C
IT
ANCE
(
p
F
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
=
C
GD
0
2
4
6
8
10
0
5
10
15
20
V
GS
, G
A
T
E
T
O
S
O
URCE
V
O
L
T
A
G
E
(
V
)
Q
g
, GATE CHARGE (nC)
V
DD
= 15V
I
D
= 35A
I
D
= 1A
WAVEFORMS IN
DESCENDING ORDER:
2005 Fairchild Semiconductor Corporation
FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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7
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
L
V
DD
Q
g(TH)
V
GS
= 1V
Q
gs2
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
Q
g(5)
V
GS
= 5V
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
2005 Fairchild Semiconductor Corporation
FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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8
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application's ambient
temperature, T
A
(
o
C), and thermal resistance R
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part's current and maximum
power dissipation ratings. Precise determination of P
DM
is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer's preliminary application evaluation. Figure 21
defines the R
JA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
(EQ. 1)
P
D M
T
JM
T
A
(
)
R
JA
-----------------------------
=
Area in Inches Squared
(EQ. 2)
R
JA
33.32
23.84
0.268
Area
+
(
)
-------------------------------------
+
=
(EQ. 3)
R
JA
33.32
154
1.73
Area
+
(
)
----------------------------------
+
=
Area in Centimeters Squared
25
50
75
100
125
0.01
0.1
1
10
Figure 21. Thermal Resistance vs Mounting
Pad Area
R
JA
= 33.32+ 23.84/(0.268+Area) EQ.2
R
JA
(
o
C/W
)
AREA, TOP COPPER AREA in
2
(cm
2
)
R
JA
= 33.32+ 154/(1.73+Area) EQ.3
(0.645)
(6.45)
(64.5)
(0.0645)
2005 Fairchild Semiconductor Corporation
FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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9
PSPICE Electrical Model
.SUBCKT FDD8878 2 1 3 ; rev February 2004
Ca 12 8 8.6e-10
Cb 15 14 7.2e-10
Cin 6 8 8e-10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 32.97
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.4e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2e-9
RLgate 1 9 54
RLdrain 2 5 10
RLsource 3 7 20
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 6.9e-3
Rgate 9 20 3.1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2.7e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*125),5))}
.MODEL DbodyMOD D (IS=2.6E-12 IKF=8 N=1.01 RS=6.4e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=3.4e-10 M=0.53 TT=1e-17 XTI=2)
.MODEL DbreakMOD D (RS=1.4 TRS1=1e-3 TRS2=-5e-6)
.MODEL DplcapMOD D (CJO=3.4e-10 IS=1e-30 N=10 M=0.39)
.MODEL MmedMOD NMOS (VTO=1.75 KP=7 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.1 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=2.2 KP=100 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=1.45 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=31 RS=0.1 T_ABS=25)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)
.MODEL RdrainMOD RES (TC1=1e-4 TC2=7.5e-6)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=1.3e-2 TC2=2e-6)
.MODEL RvthresMOD RES (TC1=-1.7e-3 TC2=-8e-6)
.MODEL RvtempMOD RES (TC1=-2.2e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.5 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4.5)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=-2)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
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RBREAK
RVTEMP
VBAT
RVTHRES
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S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
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8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
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21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
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-
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SABER Electrical Model
rev February 2004
template FDD8878 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=2.6e-12,ikf=8,nl=1.01,rs=6.4e-3,trs1=8e-4,trs2=2e-7,cjo=3.4e-10,m=0.53,tt=1e-17,xti=2)
dp..model dbreakmod = (rs=1.4,trs1=1e-3,trs2=-5e-6)
dp..model dplcapmod = (cjo=3.4e-10,isl=10e-30,nl=10,m=0.39)
m..model mmedmod = (type=_n,vto=1.75,kp=7,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.2,kp=100,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.45,kp=0.03,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.5,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4.5)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1,voff=-2)
c.ca n12 n8 = 8.6e-10
c.cb n15 n14 = 7.2e-10
c.cin n6 n8 = 8e-10
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 32.97
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.4e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2e-9
res.rlgate n1 n9 = 54
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 20
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7
res.rdrain n50 n16 = 6.9e-3, tc1=1e-4,tc2=7.5e-6
res.rgate n9 n20 = 3.1
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.7e-3, tc1=1.3e-2,tc2=2e-6
res.rvthres n22 n8 = 1, tc1=-1.7e-3,tc2=-8e-6
res.rvtemp n18 n19 = 1, tc1=-2.2e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/125))** 5))
}
}
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RVTEMP
VBAT
RVTHRES
IT
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S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
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8
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13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
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+
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FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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PSPICE Thermal Model
REV 23 February 2004
FDD8878T
CTHERM1 TH 6 3.5e-4
CTHERM2 6 5 5e-4
CTHERM3 5 4 2.5e-3
CTHERM4 4 3 2.7e-3
CTHERM5 3 2 5e-3
CTHERM6 2 TL 1e-2
RTHERM1 TH 6 2.9e-1
RTHERM2 6 5 3.5e-1
RTHERM3 5 4 4.5e-1
RTHERM4 4 3 5.2e-1
RTHERM5 3 2 6.9e-1
RTHERM6 2 TL 7e-1
SABER Thermal Model
SABER thermal model FDD8878T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.5e-4
ctherm.ctherm2 6 5 =5e-4
ctherm.ctherm3 5 4 =2.5e-3
ctherm.ctherm4 4 3 =2.7e-3
ctherm.ctherm5 3 2 =5e-3
ctherm.ctherm6 2 tl =1e-2
rtherm.rtherm1 th 6 =2.9e-1
rtherm.rtherm2 6 5 =3.5e-1
rtherm.rtherm3 5 4 =4.5e-1
rtherm.rtherm4 4 3 =5.2e-1
rtherm.rtherm5 3 2 =6.9e-1
rtherm.rtherm6 2 tl =7e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
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CASE
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FDD8878 / FDU8878 Rev. A3
www.fairchildsemi.com
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