2002 Fairchild Semiconductor Corporation
October 2002
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
FDB3652 / FDP3652 / FDI3652
N-Channel PowerTrench
MOSFET
100V, 61A, 16m
Features
r
DS(ON)
= 14m
(Typ.), V
GS
= 10V, I
D
= 61A
Q
g
(tot) = 41nC (Typ.), V
GS
= 10V
Low Miller Charge
Low Q
RR
Body Diode
UIS Capability (Single Pulse and Repetitive Pulse)
Qualified to AEC Q101
Formerly developmental type 82769
Applications
DC/DC Converters and Off-line UPS
Distributed Power Architectures and VRMs
Primary Switch for 24V and 48V Systems
High Voltage Synchronous Rectifier
Direct Injection / Diesel Injection Systems
42V Automotive Load Control
Electronic Valve Train Systems
MOSFET Maximum Ratings
T
C
= 25C unless otherwise noted
Thermal Characteristics
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
Symbol
Parameter
Ratings
Units
V
DSS
Drain to Source Voltage
100
V
V
GS
Gate to Source Voltage
20
V
I
D
Drain Current
61
A
Continuous (T
C
= 25
o
C, V
GS
= 10V)
Continuous (T
C
= 100
o
C, V
GS
= 10V)
43
A
Continuous (T
amb
= 25
o
C, V
GS
= 10V) with R
JA
= 43
o
C/W)
9
A
Pulsed
Figure 4
A
E
AS
Single Pulse Avalanche Energy (Note 1)
182
mJ
P
D
Power dissipation
150
W
Derate above 25
o
C
1.0
W/
o
C
T
J
, T
STG
Operating and Storage Temperature
-55 to 175
o
C
R
JC
Thermal Resistance Junction to Case TO-220, TO-263, TO-262
1.0
o
C/W
R
JA
Thermal Resistance Junction to Ambient TO-220, TO-263, TO-262 (Note 2)
62
o
C/W
R
JA
Thermal Resistance Junction to Ambient TO-263, 1in
2
copper pad area
43
o
C/W
D
G
S
TO-263AB
FDB SERIES
GATE
SOURCE
DRAIN
(FLANGE)
TO-220AB
DRAIN
(FLANGE)
FDP SERIES
GATE
DRAIN
SOURCE
GATE
DRAIN
SOURCE
DRAIN
(FLANGE)
TO-262AA
FDI SERIES
2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
Package Marking and Ordering Information
Electrical Characteristics
T
C
= 25C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
(V
GS
= 10V)
Drain-Source Diode Characteristics
Notes:
1: Starting T
J
= 25C, L =
0.228mH, I
AS
= 40A.
2: Pulse Width = 100s
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDB3652
FDB3652
TO-263AB
330mm
24mm
800 units
FDP3652
FDP3652
TO-220AB
Tube
N/A
50 units
FDI3652
FDI3652
TO-262AA
Tube
N/A
50 units
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
B
VDSS
Drain to Source Breakdown Voltage
I
D
= 250
A, V
GS
= 0V
105
-
-
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 80V
-
-
1
A
V
GS
= 0V
T
C
= 150
o
C
-
-
250
I
GSS
Gate to Source Leakage Current
V
GS
= 20V
-
-
100
nA
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
A
2
-
4
V
r
DS(ON)
Drain to Source On Resistance
I
D
= 61A, V
GS
= 10V
-
0.014
0.016
I
D
= 30A, V
GS
= 6V
-
0.018
0.026
I
D
= 61A, V
GS
= 10V,
T
J
= 175
o
C
-
0.035
0.043
C
ISS
Input Capacitance
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
2880
-
pF
C
OSS
Output Capacitance
-
390
-
pF
C
RSS
Reverse Transfer Capacitance
-
100
-
pF
Q
g(TOT)
Total Gate Charge at 10V
V
GS
= 0V to 10V
V
DD
= 50V
I
D
= 61A
I
g
= 1.0mA
41
53
nC
Q
g(TH)
Threshold Gate Charge
V
GS
= 0V to 2V
-
5
6.5
nC
Q
gs
Gate to Source Gate Charge
-
15
-
nC
Q
gs2
Gate Charge Threshold to Plateau
-
10
-
nC
Q
gd
Gate to Drain "Miller" Charge
-
10
-
nC
t
ON
Turn-On Time
V
DD
= 50V, I
D
= 61A
V
GS
= 10V, R
GS
= 6.8
-
-
146
ns
t
d(ON)
Turn-On Delay Time
-
12
-
ns
t
r
Rise Time
-
85
-
ns
t
d(OFF)
Turn-Off Delay Time
-
26
-
ns
t
f
Fall Time
-
45
-
ns
t
OFF
Turn-Off Time
-
-
107
ns
V
SD
Source to Drain Diode Voltage
I
SD
= 61A
-
-
1.25
V
I
SD
= 30A
-
-
1.0
V
t
rr
Reverse Recovery Time
I
SD
= 61A, dI
SD
/dt = 100A/
s
-
-
62
ns
Q
RR
Reverse Recovered Charge
I
SD
= 61A, dI
SD
/dt = 100A/
s
-
-
45
nC
2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
Typical Characteristics
T
C
= 25C unless otherwise noted
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
T
C
, CASE TEMPERATURE (
o
C)
PO
WE
R
D
I
SSI
P
A
T
I
O
N
M
U
L
T
I
P
L
I
ER
0
0
25
50
75
100
175
0.2
0.4
0.6
0.8
1.0
1.2
125
150
0
25
50
75
25
50
75
100
125
150
175
I
D
, DRAIN CURRE
N
T
(
A
)
T
C
, CASE TEMPERATURE (
o
C)
0.1
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.01
2
t , RECTANGULAR PULSE DURATION (s)
Z
JC
, NO
RM
AL
IZ
E
D
T
H
E
R
M
A
L
IM
P
E
D
ANCE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
100
1000
50
I
DM
, P
E
AK CUR
RE
NT
(
A
)
t, PULSE WIDTH (s)
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
GS
= 10V
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
T
C
= 25
o
C
2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
Figure 9. Drain to Source On Resistance vs Drain
Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
Typical Characteristics
T
C
= 25C unless otherwise noted
0.1
1
10
100
1000
1
10
100
200
I
D
, DRAIN CURRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
T
J
= MAX RATED
T
C
= 25
o
C
SINGLE PULSE
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
10
s
10ms
1ms
DC
100
s
1
10
100
0.1
1
10
0.01
500
I
AS
, A
V
AL
ANCHE
CURRE
NT
(
A
)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R 0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0
25
50
75
100
125
3
4
5
6
7
I
D
, DRAIN CURRE
NT
(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= 25
o
C
T
J
= -55
o
C
0
25
50
75
100
125
0
1
2
3
4
I
D
, DRAIN CURRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 6V
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
GS
= 5V
T
C
= 25
o
C
V
GS
= 7V
V
GS
= 10V
12
14
16
18
20
0
20
40
60
I
D
, DRAIN CURRENT (A)
V
GS
= 6V
V
GS
= 10V
DRAIN T
O
S
O
URCE
O
N
RE
S
I
S
T
ANCE
(
m
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0
0.5
1.0
1.5
2.0
2.5
3.0
-80
-40
0
40
80
120
160
200
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
T
J
, JUNCTION TEMPERATURE (
o
C)
O
N
RE
S
I
S
T
ANCE
V
GS
= 10V, I
D
= 61A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
Typical Characteristics
T
C
= 25C unless otherwise noted
0.4
0.6
0.8
1.0
1.2
1.4
-80
-40
0
40
80
120
160
200
NO
RM
AL
IZ
E
D
G
A
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250
A
T
HRE
S
H
O
L
D V
O
L
T
A
G
E
0.9
1.0
1.1
1.2
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
I
D
= 250
A
BRE
AKD
O
W
N V
O
L
T
A
G
E
100
1000
0.1
1
10
100
40
5000
C, CAP
A
C
IT
ANCE
(
p
F
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
= C
GD
0
2
4
6
8
10
0
10
20
30
40
50
V
GS
, G
A
T
E
T
O
S
O
URCE
V
O
L
T
A
G
E
(
V
)
Q
g
, GATE CHARGE (nC)
V
DD
= 50V
I
D
= 61A
I
D
= 30A
WAVEFORMS IN
DESCENDING ORDER:
2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
L
V
DD
Q
g(TH)
V
GS
= 2V
Q
gs2
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application's ambient
temperature, T
A
(
o
C), and thermal resistance R
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part's current and maximum
power dissipation ratings. Precise determination of P
DM
is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer's preliminary application evaluation. Figure 21
defines the R
JA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
(EQ. 1)
P
D M
T
JM
T
A
(
)
R
JA
-----------------------------
=
Area in Iches Squared
(EQ. 2)
R
JA
26.51
19.84
0.262
Area
+
(
)
-------------------------------------
+
=
(EQ. 3)
R
JA
26.51
128
1.69
Area
+
(
)
----------------------------------
+
=
Area in Centimeter Squared
Figure 21. Thermal Resistance vs Mounting
Pad Area
20
40
60
80
1
10
0.1
R
JA
= 26.51+ 19.84/(0.262+Area) EQ.2
R
JA
(
o
C/W
)
AREA, TOP COPPER AREA in
2
(cm
2
)
(0.645)
(6.45)
(64.5)
R
JA
= 26.51+ 128/(1.69+Area) EQ.3
2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
PSPICE Electrical Model
.SUBCKT FDP3652 2 1 3 rev March 2002
Ca 12 8 1.1e-9
Cb 15 14 1.1e-9
Cin 6 8 2.8e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 108.2
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 7.16e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.29e-9
RLgate 1 9 71.6
RLdrain 2 5 10
RLsource 3 7 22.9
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 5.7e-3
Rgate 9 20 1.06
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 6.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*150),7))}
.MODEL DbodyMOD D (IS=1.5E-11 N=1.06 RS=2.5e-3 TRS1=2.4e-3 TRS2=1.1e-6
+ CJO=1.9e-9 M=5.8e-1 TT=2.5e-8 XTI=3.9)
.MODEL DbreakMOD D (RS=2.7e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=7e-10 IS=1e-30 N=10 M=0.58)
.MODEL MmedMOD NMOS (VTO=3.6 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06)
.MODEL MstroMOD NMOS (VTO=4.3 KP=110 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06e1 RS=.1)
.MODEL RbreakMOD RES (TC1=1.05e-3 TC2=1e-6)
.MODEL RdrainMOD RES (TC1=1.7e-2 TC2=3.2e-5)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.2e-5)
.MODEL RvtempMOD RES (TC1=-3.3e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
SABER Electrical Model
REV March 2002
template FDP3652 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.5e-11,nl=1.06,rs=2.5e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.9e-9,m=5.8e-1,tt=2.5e-8,xti=3.9)
dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=7e-10,isl=10e-30,nl=10,m=0.58)
m..model mmedmod = (type=_n,vto=3.6,kp=5.5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=110,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1)
c.ca n12 n8 = 1.1e-9
c.cb n15 n14 = 1.1e-9
c.cin n6 n8 = 2.8e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 108.2
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 7.16e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.29e-9
res.rlgate n1 n9 = 71.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 22.9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=1e-6
res.rdrain n50 n16 = 5.7e-3, tc1=1.7e-2,tc2=3.2e-5
res.rgate n9 n20 = 1.06
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.2e-5
res.rvtemp n18 n19 = 1, tc1=-3.3e-3,tc2=1.3e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/150))** 7))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. B
FD
B
3
6
52
/ F
D
P
365
2 /
FD
I36
5
2
SPICE Thermal Model
REV 23 March 2002
FDP3652
CTHERM1 TH 6 1e-2
CTHERM2 6 5 1.5e-2
CTHERM3 5 4 2e-2
CTHERM4 4 3 2.1e-2
CTHERM5 3 2 2.2e-2
CTHERM6 2 TL 9e-2
RTHERM1 TH 6 2.7e-2
RTHERM2 6 5 2.8e-2
RTHERM3 5 4 7.8e-2
RTHERM4 4 3 9e-2
RTHERM5 3 2 2.7e-1
RTHERM6 2 TL 2.87e-1
SABER Thermal Model
SABER thermal model FDP3652
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1e-2
ctherm.ctherm2 6 5 =1.5e-2
ctherm.ctherm3 5 4 =2e-2
ctherm.ctherm4 4 3 =2.1e-2
ctherm.ctherm5 3 2 =2.2e-2
ctherm.ctherm6 2 tl =9e-2
rtherm.rtherm1 th 6 =2.7e-2
rtherm.rtherm2 6 5 =2.8e-2
rtherm.rtherm3 5 4 =7.8e-2
rtherm.rtherm4 4 3 =9e-2
rtherm.rtherm5 3 2 =2.7e-1
rtherm.rtherm6 2 tl =2.87e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE
Rev. I1
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
ACExTM
ActiveArrayTM
BottomlessTM
CoolFETTM
CROSSVOLTTM
DOMETM
EcoSPARKTM
E
2
CMOSTM
EnSignaTM
FACTTM
FACT Quiet SeriesTM
FAST
FASTrTM
FRFETTM
GlobalOptoisolatorTM
GTOTM
HiSeCTM
I
2
CTM
ImpliedDisconnectTM
ISOPLANARTM
LittleFETTM
MicroFETTM
MicroPakTM
MICROWIRETM
MSXTM
MSXProTM
OCXTM
OCXProTM
OPTOLOGIC
OPTOPLANARTM
PACMANTM
POPTM
Power247TM
PowerTrench
QFETTM
QSTM
QT OptoelectronicsTM
Quiet SeriesTM
RapidConfigureTM
RapidConnectTM
SILENT SWITCHER
SMART STARTTM
SPMTM
StealthTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
SyncFETTM
TinyLogicTM
TruTranslationTM
UHCTM
UltraFET
VCXTM
Across the board. Around the world.TM
The Power FranchiseTM
Programmable Active DroopTM
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
PDF 
ZIP