February 2003
2003 Fairchild Semiconductor Corporation
FDM3300NZ Rev. E3 (W)
FDM3300NZ
Monolithic Common Drain N-Channel 2.5V Specified PowerTrench
MOSFET
General Description
This dual N-Channel MOSFET has been designed
using Fairchild Semiconductor's advanced Power
Trench process to optimize the R
DS(ON)
@ V
GS
= 2.5v on
special MicroFET lead frame with all the drains on one
side of the package.
Applications
Li-Ion Battery Pack
Features
10 A, 20 V
R
DS(ON)
= 23 m
@ V
GS
= 4.5 V
R
DS(ON)
= 28 m
@ V
GS
= 2.5 V
> 2000v ESD Protection
Low Profile 1mm maximum in the new package
MicroFET 3.3x3.3 mm
5
4
6
3
7
2
8
1
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol
Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
20
V
V
GSS
Gate-Source Voltage
12
V
I
D
Drain Current Continuous
(Note 1a)
10
A
Pulsed
40
P
D
Power Dissipation (Steady State)
(Note 1a)
2.5
W
(Note 1b)
1.2
T
J
, T
STG
Operating and Storage Junction Temperature Range
55 to +150
C
Thermal Characteristics
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
52
C/W
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1b)
108
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
5
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
3300N
FDM3300NZ
7''
12mm
3000 units
F
D
M
3
3
0
0
N
Z
MicroFET
D1
D2
D2
D1
D1
D2
D2
D1
S1
G1
S2
G2
D1
D2
D2
D1
D1
D2
D2
D1
S1
G1
S2
G2
FDM3300NZ Rev E3 (W)
Electrical Characteristics
T
A
= 25C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BV
DSS
DrainSource Breakdown
Voltage
V
GS
= 0 V,
I
D
= 250
A
20
V
BV
DSS
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250
A, Referenced to 25
C
10.7
mV/
C
I
DSS
Zero Gate Voltage Drain Current V
DS
= 16 V,
V
GS
= 0 V
1
A
I
GSS
GateBody Leakage,
V
GS
=
12 V, V
DS
= 0 V
10
A
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
,
I
D
= 250
A
0.6
0.9
1.5
V
V
GS(th)
T
J
Gate Threshold Voltage
Temperature Coefficient
I
D
= 250
A, Referenced to 25
C
3
mV/
C
R
DS(on)
Static DrainSource
OnResistance
V
GS
= 4.5 V,
I
D
= 10A
V
GS
= 2.5 V,
I
D
= 9 A
V
GS
= 4.5 V, I
D
= 10A, T
J
=125
C
16
20
22
23
28
31
m
I
D(on)
OnState Drain Current
V
GS
= 2.5 V,
V
DS
= 5 V
10
A
g
FS
Forward Transconductance
V
DS
= 5 V,
I
D
=10 A
35
S
Dynamic Characteristics
C
iss
Input Capacitance
1210
pF
C
oss
Output Capacitance
330
pF
C
rss
Reverse Transfer Capacitance
V
DS
= 10 V,
V
GS
= 0 V,
f = 1.0 MHz
180
pF
R
G
Gate Resistance
V
GS
= 0 V,
f = 1.0 MHz
2.3
Switching Characteristics
(Note 2)
t
d(on)
TurnOn Delay Time
10
20
ns
t
r
TurnOn Rise Time
14
25
ns
t
d(off)
TurnOff Delay Time
26
42
ns
t
f
TurnOff Fall Time
V
DD
= 10 V,
I
D
= 1 A,
V
GS
= 4.5 V,
R
GEN
= 6
13
23
ns
Q
g
Total Gate Charge
12
17
nC
Q
gs
GateSource Charge
2
nC
Q
gd
GateDrain Charge
V
DS
= 10 V,
I
D
= 10 A,
V
GS
= 4.5 V
4
nC
DrainSource Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous DrainSource Diode Forward Current
2
A
V
SD
DrainSource Diode Forward
Voltage
V
GS
= 0 V, I
S
= 2 A
(Note 2)
0.7
1.2
V
t
rr
Diode Reverse Recovery Time
20
nS
Q
rr
Diode Reverse Recovery Charge
I
F
= 10 A,
d
iF
/d
t
= 100 A/s
6
nC
Notes:
1.
R
JA
is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
JC
are guaranteed by design while R
JA
is
determined by the user's board design.
(a).
R
JA
= 52C/W when mounted on a 1in
2
pad of 2 oz copper, 1.5" x 1.5" x 0.062" thick PCB
(b).
R
JA
= 108C/W when mounted on a minimum pad of 2 oz copper
2.
Pulse Test: Pulse Width < 300
s, Duty Cycle < 2.0%
F
D
M
3
3
0
0
N
Z
FDM3300NZ Rev E3 (W)
Typical Characteristics
0
10
20
30
40
0
0.5
1
1.5
2
V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
,
D
R
A
I
N
C
U
R
R
E
N
T
(
A
)
2.5V
2.0V
V
GS
= 4.5V
3.0V
3.5V
0.8
1
1.2
1.4
1.6
1.8
2
0
4
8
12
16
20
I
D
, DRAIN CURRENT (A)
R
D
S
(
O
N
)
,
N
O
R
M
A
L
I
Z
E
D
D
R
A
I
N
-
S
O
U
R
C
E
O
N
-
R
E
S
I
S
T
A
N
C
E
V
GS
= 2.0V
2.5V
3.5V
4.5V
3.0V
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.6
0.8
1
1.2
1.4
1.6
-50
-25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (
o
C)
R
D
S
(
O
N
)
,
N
O
R
M
A
L
I
Z
E
D
D
R
A
I
N
-
S
O
U
R
C
E
O
N
-
R
E
S
I
S
T
A
N
C
E
I
D
= 10A
V
GS
= 4.5V
0.012
0.017
0.022
0.027
0.032
0.037
0.042
0.047
1
2
3
4
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
R
D
S
(
O
N
)
,
O
N
-
R
E
S
I
S
T
A
N
C
E
(
O
H
M
)
I
D
= 5A
T
A
= 125
o
C
T
A
= 25
o
C
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
10
20
30
40
0.5
1
1.5
2
2.5
3
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
,
D
R
A
I
N
C
U
R
R
E
N
T
(
A
)
T
A
= -55
o
C
25
o
C
125
o
C
V
DS
= 5V
0.0001
0.001
0.01
0.1
1
10
100
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
I
S
,
R
E
V
E
R
S
E
D
R
A
I
N
C
U
R
R
E
N
T
(
A
)
T
A
= 125
o
C
25
o
C
-55
o
C
V
GS
= 0V
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
F
D
M
3
3
0
0
N
Z
FDM3300NZ Rev E3 (W)
Typical Characteristics
0
1
2
3
4
5
0
3
6
9
12
15
Q
g
, GATE CHARGE (nC)
V
G
S
,
G
A
T
E
-
S
O
U
R
C
E
V
O
L
T
A
G
E
(
V
)
I
D
= 10A
V
DS
= 5V
15V
10V
0
300
600
900
1200
1500
1800
0
4
8
12
16
20
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
C
A
P
A
C
I
T
A
N
C
E
(
p
F
)
C
iss
C
rss
C
oss
f = 1MHz
V
GS
= 0 V
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.1
1
10
100
V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
,
D
R
A
I
N
C
U
R
R
E
N
T
(
A
)
DC
10s
1s
100ms
R
DS(ON)
LIMIT
V
GS
= 4.5V
SINGLE PULSE
R
JA
= 108
o
C/W
T
A
= 25
o
C
10ms
1ms
100us
0
10
20
30
40
50
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
P
(
p
k
)
,
P
E
A
K
T
R
A
N
S
I
E
N
T
P
O
W
E
R
(
W
)
SINGLE PULSE
R
JA
= 108C/W
T
A
= 25C
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
r
(
t
)
,
N
O
R
M
A
L
I
Z
E
D
E
F
F
E
C
T
I
V
E
T
R
A
N
S
I
E
N
T
T
H
E
R
M
A
L
R
E
S
I
S
T
A
N
C
E
R
JA
(t) = r(t) * R
JA
R
JA
=108 C/W
T
J
- T
A
= P * R
JA
(t)
Duty Cycle, D = t
1
/ t
2
P(pk)
t
1
t
2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
F
D
M
3
3
0
0
N
Z
FDM3300NZ Rev E3 (W)
PSPICE Electrical Model N-Channel
.SUBCKT FDM3300NZ 2 1 3
*NOM TEMP=25 DEG C
*FEB 26, 2003
CA 12 8 1E-9
CB 15 14 1.2E-9
CIN 6 8 10.8E-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 23.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LGATE 1 9 3.84E-9
LDRAIN 2 5 1.00E-9
LSOURCE 3 7 4E-9
RLGATE 1 9 38.4
RLDRAIN 2 5 10
RLSOURCE 3 7 40
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 8.3E-3
RGATE 9 20 4.2
RSLC1 5 51 RSLCMOD 1E-6
RSLC2 5 50 1E3
RSOURCE 8 7 RSOURCEMOD 3.9E-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*115),3))}
.MODEL DBODYMOD D (IS=2E-12 RS=9.9E-3 N=0.90 TRS1=2.1E-3 TRS2=1.0E-6 CJO=4.5E-10 TT=1E-9 M=0.45 IKF=0.3 XTI=2.0)
.MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6)
.MODEL DPLCAPMOD D (CJO=45E-11 IS=1E-30 N=10 M=0.4)
.MODEL MMEDMOD NMOS (VTO=1.05 KP=8 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2)
.MODEL MSTROMOD NMOS (VTO=1.31 KP=82 IS=1E-30 N=10 TOX=1 L=1U W=1U)
.MODEL MWEAKMOD NMOS (VTO=0.81 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1)
.MODEL RBREAKMOD RES (TC1=0.56E-3 TC2=1.00E-7)
.MODEL RDRAINMOD RES (TC1=4.6E-3 TC2=10E-6)
.MODEL RSLCMOD RES (TC1=2.5E-3 TC2=8E-6)
.MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6)
.MODEL RVTHRESMOD RES (TC1=-1.85E-3 TC2=-7E-6)
.MODEL RVTEMPMOD RES (TC1=-0.7E-3 TC2=0.50E-6)
.MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.0 VOFF=0.6)
.MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=0.6 VOFF=-1.0)
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET
Featuring Global Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by
William J. Hepp and C. Frank Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
F
D
M
3
3
0
0
N
Z
FDM3300NZ Rev E3 (W)
SPICE Thermal Model
.SUBCKT FDM3300NZ_THERM TH TL
*Thermal Model Subcircuit
*Feb 26, 2003
CTHERM1 TH 8 3
CTHERM2 8 7 5
CTHERM3 7 6 7
CTHERM4 6 5 13.2
CTHERM5 5 4 25.4
CTHERM6 4 3 36.21
CTHERM7 3 2 47.54
CTHERM8 2 TL 208.21
RTHERM1 TH 8 0.04
RTHERM2 8 7 0.05
RTHERM3 7 6 0.06
RTHERM4 6 5 0.07
RTHERM5 5 4 0.085
RTHERM6 4 3 0.095
RTHERM7 3 2 0.25
RTHERM8 2 TL 0.35
.ENDS
F
D
M
3
3
0
0
N
Z
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
7
JUNCTION
AMBIENT
8
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
FDM3300NZ Rev E3 (W)
Dimensional Outline and Pad Layout
F
D
M
3
3
0
0
N
Z
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
ImpliedDisconnect
ISOPLANAR
LittleFET
MicroFET
MicroPak
MICROWIRE
MSX
MSXPro
OCX
OCXPro
OPTOLOGIC
OPTOPLANAR
FACT
FACT Quiet Series
FAST
FASTr
FRFET
GlobalOptoisolator
GTO
HiSeC
I
2
C
Rev. I2
ACEx
ActiveArray
Bottomless
CoolFET
CROSSVOLT
DOME
EcoSPARK
E
2
CMOS
TM
EnSigna
TM
PACMAN
POP
Power247
PowerTrench
QFET
QS
QT Optoelectronics
Quiet Series
RapidConfigure
RapidConnect
SILENT SWITCHER
SMART START
SPM
Stealth
SuperSOT-3
SuperSOT-6
SuperSOT-8
SyncFET
TinyLogic
TruTranslation
UHC
UltraFET
VCX
Across the board. Around the world.
The Power Franchise
Programmable Active Droop
PDF 
ZIP