2005 Fairchild Semiconductor Corporation
FDM3622 Rev. A
January 2005
www.fairchildsemi.com
F
D
M362
2 N
-
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SF
ET
1
FDM3622
N-Channel PowerTrench
MOSFET
100V, 4.4A, 60m
Features
r
DS(ON)
= 44m
(Typ.), V
GS
= 10V, I
D
= 4.4A
Q
g
(tot) = 13nC (Typ.), V
GS
= 10V
Low Miller Charge
Low Q
RR
Body Diode
Optimized efficiency at high frequencies
UIS Capability (Single Pulse and Repetitive Pulse)
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor's advanced PowerTrench process that has
been especially tailored to minimize the on-state resistance
and yet maintain low gate charge for superior switching
performance.
Applications
Distributed Power Architectures and VRMs
Primary Switch for 24V and 48V Systems
High Voltage Synchronous Rectifier
Formerly developmental type 82744
1
2
3
4
8
7
6
5
MicroFET 3.3 x 3.3
2005 Fairchild Semiconductor Corporation
FDM3622 Rev. A
www.fairchildsemi.com
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MOSFET Maximum Ratings
T
C
= 25C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Electrical Characteristics
T
C
= 25C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Symbol
Parameter
Ratings
Units
V
DSS
Drain to Source Voltage
100
V
V
GS
Gate to Source Voltage
20
V
I
D
Drain Current
4.4
A
Continuous (T
C
= 25
o
C, V
GS
= 10V, R
JA
= 52
o
C/W)
Continuous (T
C
= 25
o
C, V
GS
= 6V, R
JA
= 52
o
C/W)
3.8
Continuous (T
C
= 100
o
C, V
GS
= 10V, R
JA
= 52
o
C/W)
2.8
A
Pulsed
Figure 4
A
E
AS
Single Pulse Avalanche Energy (Note 2)
190
mJ
P
D
Power dissipation
2.4
W
Derate above 25
o
C
19
mW/
o
C
T
J
, T
STG
Operating and Storage Temperature
-55 to 150
o
C
R
JA
Thermal Resistance Junction to Ambient (Note 1a)
52
o
C/W
R
JA
Thermal Resistance Junction to Ambient (Note 1b)
108
o
C/W
R
JC
Thermal Resistance Junction to Case (Note 1)
1.8
o
C/W
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDM3622
FDM3622
MicroFET3.3x3.3
7"
12mm
3000 units
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
B
VDSS
Drain to Source Breakdown Voltage
I
D
= 250
A, V
GS
= 0V
100
-
-
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 80V
-
-
1
A
V
GS
= 0V
T
C
= 100
o
C
-
-
250
I
GSS
Gate to Source Leakage Current
V
GS
=
20V
-
-
100
nA
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
A
2
-
4
V
r
DS(ON)
Drain to Source On Resistance
I
D
= 4.4A, V
GS
= 10V
-
0.044
0.060
I
D
= 3.8A, V
GS
= 6V,
-
0.056
0.080
I
D
= 4.4A, V
GS
= 10V,
T
C
= 150
o
C
-
0.092
0.120
C
ISS
Input Capacitance
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
820
-
pF
C
OSS
Output Capacitance
-
125
-
pF
C
RSS
Reverse Transfer Capacitance
-
35
-
pF
R
G
Gate Resistance
V
GS
= 0.5V, f = 1MHz
-
3.1
-
Q
g(TOT)
Total Gate Charge at 10V
V
GS
= 0V to 10V
V
DD
= 50V
I
D
= 4.4A
I
g
= 1.0mA
-
13
17
nC
Q
g(TH)
Threshold Gate Charge
V
GS
= 0V to 2V
-
1.6
2.1
nC
Q
gs
Gate to Source Gate Charge
-
3.6
-
nC
Q
gs2
Gate Charge Threshold to Plateau
-
2.0
-
nC
Q
gd
Gate to Drain "Miller" Charge
-
3.4
-
nC
2005 Fairchild Semiconductor Corporation
FDM3622 Rev. A
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Resistive Switching Characteristics
(V
GS
= 10V)
Drain-Source Diode Characteristics
Notes:
1. R
JA
is determined with the device mounted on a 1in
2
2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
JC
is guaranteed by design while R
JA
is
determined by the user's board design.
(a). R
JA
= 52C/W when mounted on a 1in
2
pad of 2 oz. copper.
(b). R
JA
= 108C/W when mounted on a minimum pad of 2 oz. copper
2. Starting T
J
= 25C, L = 31mH, I
AS
= 3.5A, V
DD
= 100V
t
ON
Turn-On Time
V
DD
= 50V, I
D
= 4.4A
V
GS
= 10V, R
GS
= 24
-
-
54
ns
t
d(ON)
Turn-On Delay Time
-
11
-
ns
t
r
Rise Time
-
25
-
ns
t
d(OFF)
Turn-Off Delay Time
-
35
-
ns
t
f
Fall Time
-
26
-
ns
t
OFF
Turn-Off Time
-
-
92
ns
V
SD
Source to Drain Diode Voltage
I
SD
= 4.4A
-
-
1.25
V
I
SD
= 2.2A
-
-
1.0
V
t
rr
Reverse Recovery Time
I
SD
= 4.4A, dI
SD
/dt = 100A/
s
-
-
56
ns
Q
RR
Reverse Recovered Charge
I
SD
= 4.4A, dI
SD
/dt = 100A/
s
-
-
108
nC
2005 Fairchild Semiconductor Corporation
FDM3622 Rev. A
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Typical Characteristics
T
C
= 25C unless otherwise noted
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
T
A
, AMBIENT TEMPERATURE (
o
C)
P
O
W
E
R DIS
S
IP
A
T
IO
N M
U
L
T
IP
L
I
E
R
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
0
2
4
6
25
50
75
100
125
150
I
D
,
D
RAIN CURRE
NT
(
A
)
T
A
, AMBIENT TEMPERATURE (
o
C)
V
GS
= 10V
0.01
0.1
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
2
t , RECTANGULAR PULSE DURATION (s)
Z
JA
, NO
RM
A
L
IZ
E
D
T
H
E
R
M
A
L
IM
P
E
D
ANCE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JA
x R
JA
+ T
A
P
DM
t
1
t
2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
10
100
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
3
200
I
DM
, P
E
A
K
C
URRE
NT
(
A
)
t , PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
GS
= 10V
T
A
= 25
o
C
I = I
25
150 - T
A
125
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
2005 Fairchild Semiconductor Corporation
FDM3622 Rev. A
www.fairchildsemi.com
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Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
Typical Characteristics
T
C
= 25C unless otherwise noted
0.1
1
10
100
1
10
120
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRE
NT
(
A
)
T
J
= MAX RATED
T
A
= 25
o
C
SINGLE PULSE
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
1ms
100
s
10ms
1
10
0.001
0.01
0.1
1
10
100
20
I
AS
, A
V
AL
ANCHE
CURRE
NT
(
A
)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0
2
4
6
8
10
3.0
3.5
4.0
4.5
5.0
5.5
6.0
I
D
, DRAIN CURRE
NT
(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 150
o
C
T
J
= 25
o
C
T
J
= -55
o
C
0
2
4
6
8
10
0
0.5
1.0
1.5
2.0
2.5
3.0
I
D
, DRAIN CURRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
GS
= 4.5V
T
A
= 25
o
C
V
GS
= 5V
V
GS
= 10V
V
GS
= 4.7V
40
50
60
70
80
4
6
8
10
I
D
= 0.2A
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 4.4A
r
DS
(
O
N)
, DRAIN T
O
S
O
URCE
O
N
RE
S
I
S
T
ANCE
(
m
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0
0.5
1.0
1.5
2.0
2.5
-80
-40
0
40
80
120
160
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
T
J
, JUNCTION TEMPERATURE (
o
C)
O
N
RE
S
I
S
T
ANC
E
V
GS
= 10V, I
D
= 4.4A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
2005 Fairchild Semiconductor Corporation
FDM3622 Rev. A
www.fairchildsemi.com
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Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
Typical Characteristics
T
C
= 25C unless otherwise noted
0.6
0.8
1.0
1.2
-80
-40
0
40
80
120
160
NO
RM
AL
IZ
E
D
G
A
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250
A
T
HRE
S
H
O
L
D V
O
L
T
A
G
E
0.9
1.0
1.1
1.2
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
I
D
= 250
A
BRE
AKDO
W
N
V
O
L
T
A
G
E
10
100
1000
0.1
1
10
100
1200
C, CAP
A
C
IT
ANCE
(
p
F
)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
=
C
GD
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0
2
4
6
8
10
0
3
6
9
12
15
V
GS
, G
A
T
E
T
O
S
O
URCE
V
O
L
T
A
G
E
(
V
)
Q
g
, GATE CHARGE (nC)
V
DD
= 50V
I
D
= 4.4A
I
D
= 1A
WAVEFORMS IN
DESCENDING ORDER:
2005 Fairchild Semiconductor Corporation
FDM3622 Rev. A
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Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
L
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
Q
gs2
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
2005 Fairchild Semiconductor Corporation
FDM3622 Rev. A
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PSPICE Electrical Model
.SUBCKT FDM3622 2 1 3 ;
rev October 2004
Ca 12 8 2.5e-10
Cb 15 14 2.5e-10
Cin 6 8 8e-10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 109
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 1.06e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 0.19e-9
RLgate 1 9 10.6
RLdrain 2 5 10
RLsource 3 7 1.9
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 9e-3
Rgate 9 20 3.16
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 27.7e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),2.5))}
.MODEL DbodyMOD D (IS=1.2E-12 RS=9.4e-3 TRS1=2.0e-3 TRS2=4.5e-7
+ CJO=5.5e-10 M=0.56 TT=4.4e-8 XTI=4.0)
.MODEL DbreakMOD D (RS=0.6 TRS1=1.4e-3 TRS2=-5e-5)
.MODEL DplcapMOD D (CJO=2.0e-10 IS=1.0e-30 N=10 M=0.54)
.MODEL MmedMOD NMOS (VTO=3.58 KP=2.8 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.16)
.MODEL MstroMOD NMOS (VTO=4.26 KP=32 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.12 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=31.6 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.05e-3 TC2=-1.1e-8)
.MODEL RdrainMOD RES (TC1=3.0e-2 TC2=5e-5)
.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.9e-6)
.MODEL RsourceMOD RES (TC1=1.0e-3 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.4e-5)
.MODEL RvtempMOD RES (TC1=-3.4e-3 TC2=1.8e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-6.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
2005 Fairchild Semiconductor Corporation
FDM3622 Rev. A
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SABER Electrical Model
REV October 2004
ttemplate FDM3622 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.2e-12,rs=9.4e-3,trs1=2.0e-3,trs2=4.5e-7,cjo=5.5e-10,m=0.56,tt=4.4e-8,xti=4.0)
dp..model dbreakmod = (rs=0.6,trs1=1.4e-3,trs2=-5.0e-5)
dp..model dplcapmod = (cjo=2.0e-10,isl=10.0e-30,nl=10,m=0.54)
m..model mmedmod = (type=_n,vto=3.58,kp=2.8,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.26,kp=32,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.12,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-6.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5)
c.ca n12 n8 = 2.5e-10
c.cb n15 n14 = 2.5e-10
c.cin n6 n8 = 8e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 109
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 1.06e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 0.19e-9
res.rlgate n1 n9 = 10.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 1.9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=-1.1e-8
res.rdrain n50 n16 = 9e-3, tc1=3.0e-2,tc2=5e-5
res.rgate n9 n20 = 3.16
res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=2.9e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 27.7e-3, tc1=1.0e-3,tc2=1.0e-6
res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-3.4e-3,tc2=1.8e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 2.5))
}
}
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RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
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FDM3622 Rev. A
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SPICE Thermal Model
REV October 2004
FDM3622_JA Junction Ambient
Copper Area = 1sq.in
CTHERM1 TH c2 1.1e-4
CTHERM2 c2 c3 1.2e-4
CTHERM3 c3 c4 3.0e-4
CTHERM4 c4 c5 2.0e-3
CTHERM5 c5 c6 6.4e-3
CTHERM6 c6 c7 3.2e-2
CTHERM7 c7 c8 2.9e-1
CTHERM8 c8 Ambient 3
RTHERM1 TH c2 2.0e-2
RTHERM2 c2 c3 1.3e-1
RTHERM3 c3 c4 2.0e-1
RTHERM4 c4 c5 1.1
RTHERM5 c5 c6 3.3
RTHERM6 c6 c7 6.8
RTHERM7 c7 c8 12.2
RTHERM8 c8 Ambient 27
SABER Thermal Model
SABER thermal model FDM3622
Copper Area = 1sq.in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th c2 =1.1e-4
ctherm.ctherm2 c2 c3 =1.2e-4
ctherm.ctherm3 c3 c4 =3.0e-4
ctherm.ctherm4 c4 c5 =2.0e-3
ctherm.ctherm5 c5 c6 =6.4e-3
ctherm.ctherm6 c6 c7 =3.2e-2
ctherm.ctherm7 c7 c8 =2.9e-1
ctherm.ctherm8 c8 tl =3
rrtherm.rtherm1 th c2 =2.0e-2
rtherm.rtherm2 c2 c3 =1.3e-1
rtherm.rtherm3 c3 c4 =2.0e-1
rtherm.rtherm4 c4 c5 =1.1
rtherm.rtherm5 c5 c6 =3.3
rtherm.rtherm6 c6 c7 =6.8
rtherm.rtherm7 c7 c8 =12.2
rtherm.rtherm8 c8 tl =27
}
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
8
7
6
5
4
3
JUNCTION
AMBIENT
2
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
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Definition of Terms
ACExTM
ActiveArrayTM
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CoolFETTM
CROSSVOLTTM
DOMETM
EcoSPARKTM
E
2
CMOSTM
EnSignaTM
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Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
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This datasheet contains specifications on a product
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The datasheet is printed for reference information only.
FDM3622 Rev. A
www.fairchildsemi.com
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