March 1998
FDN337N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
Absolute Maximum Ratings
T
A
= 25
o
C unless other wise noted
Symbol
Parameter
FDN337N
Units
V
DSS
Drain-Source Voltage
30
V
V
GSS
Gate-Source Voltage - Continuous
8
V
I
D
Drain/Output Current - Continuous
2.2
A
- Pulsed
10
P
D
Maximum Power Dissipation
(Note 1a)
0.5
W
(Note 1b)
0.46
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
250
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
75
C/W
FDN337N Rev.C
2.2 A, 30 V, R
DS(ON)
= 0.065
@ V
GS
= 4.5 V
R
DS(ON)
= 0.082
@ V
GS
= 2.5 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOT
TM
-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SuperSOT
TM
-3 N-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
G
D
S
SuperSOT -3
TM
337
D
S
G
1998 Fairchild Semiconductor Corporation
Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 A
30
V
BV
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
I
D
= 250 A, Referenced to 25
o
C
41
mV/
o
C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
1
A
T
J
= 55C
10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 8 V,V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -8 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 A
0.4
0.7
1
V
V
GS(th)
/
T
J
Gate Threshold Voltage Temp. Coefficient
I
D
= 250 A, Referenced to 25
o
C
-2.3
mV/
o
C
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 4.5 V, I
D
= 2.2 A
0.054
0.065
T
J
=125C
0.08
0.11
V
GS
= 2.5 V, I
D
= 2 A
0.07
0.082
I
D(ON)
On-State Drain Current
V
GS
= 4.5 V, V
DS
= 5 V
10
A
g
FS
Forward Transconductance
V
DS
= 5 V, I
D
= 2.2 A
13
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
300
pF
C
oss
Output Capacitance
145
pF
C
rss
Reverse Transfer Capacitance
35
pF
SWITCHING CHARACTERISTICS
(Note)
t
D(on)
Turn - On Delay Time
V
DD
= 5 V, I
D
= 1 A,
V
GS
= 4.5 V, R
GEN
= 6
4
10
ns
t
r
Turn - On Rise Time
10
18
ns
t
D(off)
Turn - Off Delay Time
17
28
ns
t
f
Turn - Off Fall Time
4
10
ns
Q
g
Total Gate Charge
V
DS
= 10 V, I
D
= 2.2 A,
V
GS
= 4.5 V
7
9
nC
Q
gs
Gate-Source Charge
1.1
nC
Q
gd
Gate-Drain Charge
1.9
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
0.42
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 0.42 A
(Note)
0.65
1.2
V
Note:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
Typical R
JA
using the board layouts shown below on FR-4 PCB in a still air environment :
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
FDN337N Rev.C
a. 250
o
C/W when mounted on a
0.02 in
2
pad of 2oz Cu.
b. 270
o
C/W when mounted on
a 0.001 in
2
pad of 2oz Cu.
FDN337N Rev.C
0
0.3
0.6
0.9
1.2
1.5
0
1
2
3
4
5
6
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
2.5
V = 4.5V
GS
2.0
1.5
DS
D
3.0
0
1
2
3
4
5
6
0.8
1
1.2
1.4
1.6
1.8
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 2.0V
GS
3.5
3.0
4.5
D
2.5
R
DS(ON
)
, NORMALIZED
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate
-50
-25
0
25
50
75
100
125
150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
V = 4.5 V
GS
I = 2.2A
D
R , NORMALIZED
DS(ON)
Figure 3. On-Resistance Variation
with Temperature.
0
0.5
1
1.5
2
2.5
0
1
2
3
4
5
6
7
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25C
125C
V = 5.0V
DS
GS
D
T = -55C
J
Figure 5. Transfer Characteristics.
0
0.2
0.4
0.6
0.8
1
0.0001
0.001
0.01
0.1
0.5
2
4
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V = 0V
GS
SD
S
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
1
2
3
4
5
0
0.05
0.1
0.15
0.2
0.25
V , GATE TO SOURCE VOLTAGE (V)
GS
R , ON-RESISTANCE (OHM)
DS(ON)
125C
25C
I = 1.1A
D
FDN337N Rev.C
0
2
4
6
8
0
1
2
3
4
5
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 2.2A
D
15V
V = 5V
DS
10V
0.1
0.5
1
2
5
10
20
50
0.01
0.03
0.1
0.3
1
2
5
10
20
V , DRAI N-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
DC
1s
100ms
10s
1ms
RDS(ON) LIMIT
V = 4.5V
SINGLE PULSE
R =250 C/W
T = 25C
GS
A
JA
10ms
0.0001
0.001
0.01
0.1
1
10
100 300
0
10
20
30
40
50
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =270 C/W
T = 25C
JA
A
Figure 10. Single Pulse Maximum Power
Dissipation.
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1b.
Transient thermal response will change depending on the circuit board design.
0.1
0.2
0.5
1
2
5
10
20
20
50
100
200
500
1000
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C iss
f = 1 MHz
V = 0V
GS
C oss
C rss
Figure 8. Capacitance Characteristics.
Figure 7. Gate Charge Characteristics.
Figure 9. Maximum Safe Operating Area.
Typical Electrical Characteristics
(continued)
0.0001
0.001
0.01
0.1
1
10
100
300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
R (t) = r(t) * R
R = 270 C/W
Duty Cycle, D = t /t
1
2
JA
JA
JA
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
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