2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
July 2005
www.fairchildsemi.com
FDS5672 N-Channel PowerTrench
MOSFET
1
FDS5672
N-Channel PowerTrench
MOSFET
60V, 12A, 10m
Features
r
DS(ON)
= 10m
, V
GS
= 10V, I
D
= 12A
r
DS(ON)
= 14m
, V
GS
= 6V, I
D
= 10A
High performance trench technology for extremely low
r
DS(ON)
Low gate charge
High power and current handling capability
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
r
DS(ON)
and fast switching speed.
Applications
DC/DC converters
SO-8
Branding Dash
1
5
2
3
4
4
3
2
1
5
6
7
8
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
2
MOSFET Maximum Ratings
T
C
= 25C unless otherwise noted
Symbol
Parameter
Ratings
Units
V
DSS
Drain to Source Voltage
60
V
V
GS
Gate to Source Voltage
20
V
I
D
Drain Current
12
A
Continuous (T
C
= 25
o
C, V
GS
= 10V, R
JA
= 50
o
C/W)
Continuous (T
C
= 25
o
C, V
GS
= 6V, R
JA
= 50
o
C/W)
10
Pulsed
Figure 4
A
E
AS
Single Pulse Avalanche Energy (Note 1)
245
mJ
P
D
Power dissipation
2.5
W
Derate above 25
o
C
20
mW/
o
C
T
J
, T
STG
Operating and Storage Temperature
-55 to 150
o
C
Thermal Characteristics
R
JC
Thermal Resistance Junction to Case (Note 2)
25
o
C/W
R
JA
Thermal Resistance Junction to Ambient at 10 seconds (Note 3)
50
o
C/W
R
JA
Thermal Resistance Junction to Ambient at 1000 seconds (Note 3)
85
o
C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDS5672
FDS5672
SO-8
330mm
12mm
2500 units
Electrical Characteristics
T
C
= 25C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
VDSS
Drain to Source Breakdown Voltage
I
D
= 250
A, V
GS
= 0V
60
-
-
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 50V
-
-
1
A
V
GS
= 0V
T
C
= 150
o
C
-
-
250
I
GSS
Gate to Source Leakage Current
V
GS
=
20V
-
-
100
nA
On Characteristics
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
A
2
-
4
V
r
DS(ON)
Drain to Source On Resistance
I
D
= 12A, V
GS
= 10V
-
0.0088
0.010
I
D
= 10A, V
GS
= 6V,
-
0.012
0.014
I
D
= 12A, V
GS
= 10V,
T
C
= 150
o
C
-
0.016
0.023
Dynamic Characteristics
C
ISS
Input Capacitance
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
2200
-
pF
C
OSS
Output Capacitance
-
410
-
pF
C
RSS
Reverse Transfer Capacitance
-
130
-
pF
R
G
Gate Resistance
V
GS
= 0.5V, f = 1MHz
-
1.4
-
Q
g(TOT)
Total Gate Charge at 10V
V
GS
= 0V to 10V
V
DD
= 30V
I
D
= 12A
I
g
= 1.0mA
-
34
45
nC
Q
g(TH)
Threshold Gate Charge
V
GS
= 0V to 2V
-
4.2
5.5
nC
Q
gs
Gate to Source Gate Charge
-
9.4
-
nC
Q
gs2
Gate Charge Threshold to Plateau
-
5.2
-
nC
Q
gd
Gate to Drain "Miller" Charge
-
9.3
-
nC
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
3
Resistive Switching Characteristics
(V
GS
= 10V)
t
ON
Turn-On Time
V
DD
= 30V, I
D
= 12A
V
GS
= 10V, R
GS
= 9.1
-
-
50
ns
t
d(ON)
Turn-On Delay Time
-
13
-
ns
t
r
Rise Time
-
20
-
ns
t
d(OFF)
Turn-Off Delay Time
-
35
-
ns
t
f
Fall Time
-
14
-
ns
t
OFF
Turn-Off Time
-
-
64
ns
Drain-Source Diode Characteristics
V
SD
Source to Drain Diode Voltage
I
SD
= 12A
-
-
1.25
V
I
SD
= 6A
-
-
1.0
V
t
rr
Reverse Recovery Time
I
SD
=12A, dI
SD
/dt = 100A/
s
-
-
39
ns
Q
RR
Reverse Recovered Charge
I
SD
=12A, dI
SD
/dt = 100A/
s
-
-
40
nC
Notes:
1: Starting T
J
= 25C, L = 1mH, I
AS
= 22A, V
DD
= 60V, V
GS
= 10V.
2: R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. R
JC
is guaranteed by design while R
JA
is determined by the user's board design.
3: R
JA
is measured with 1.0 in
2
copper on FR-4 board.
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
4
Typical Characteristics
T
C
= 25C unless otherwise noted
Figure 1.
T
A
, AMBIENT TEMPERATURE (
o
C)
PO
WER DISSIP
A
T
I
O
N MU
L
T
I
P
LIER
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
Normalized Power Dissipation vs
Ambient Temperature
Figure 2.
0
3
6
9
12
15
25
50
75
100
125
150
I
D
,
DR
AIN CURRENT (A)
T
A
, AMBIENT TEMPERATURE (
o
C)
V
GS
= 10V
Maximum Continuous Drain Current vs
Ambient Temperature
Figure 3.
0.001
0.01
0.1
1
2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
t, RECTANGULAR PULSE DURATION (s)
Z
JA
, NORMAL
I
Z
ED
THE
R
MAL IMPE
D
A
NCE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JA
x R
JA
+ T
A
P
DM
t
1
t
2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
Normalized Maximum Transient Thermal Impedance
Figure 4.
10
100
1100
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
I
DM
, PEAK
C
URRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
GS
= 10V
T
A
= 25
o
C
I = I
25
150 - T
A
125
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
Peak Current Capability
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
5
Figure 5.
0.1
1
10
100
400
0.1
1
10
70
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURR
ENT (
A
)
T
J
= MAX RATED
T
A
= 25
o
C
SINGLE PULSE
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
1ms
100
s
10ms
Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6.
1
10
50
10
1
0.1
100
I
AS
, A
V
ALANCH
E CUR
REN
T
(
A)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
Unclamped Inductive Switching
Capability
Figure 7.
0
5
10
15
20
25
3.0
3.5
4.0
4.5
5.0
5.5
I
D
, DRAIN CURR
ENT (
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 150
o
C
T
J
= 25
o
C
T
J
= -55
o
C
Transfer Characteristics
Figure 8. Saturation Characteristics
0
5
10
20
25
0.2
0
0.4
0.6
0.8
1.0
15
I
D
, DRAIN CU
RREN
T (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
GS
= 4.5V
T
A
= 25
o
C
V
GS
= 6V
V
GS
= 10V
V
GS
= 5V
Figure 9.
5.0
7.5
10.0
12.5
15.0
0
3
6
9
12
I
D
, DRAIN CURRENT (A)
V
GS
= 6V
V
GS
= 10V
DRAIN T
O
SOURCE ON RESIST
ANCE (m
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
Drain to Source On Resistance vs Drain
Current
Figure 10.
0.5
1.0
1.5
2.0
-80
-40
0
40
80
120
160
NORMALIZED DRAIN T
O
SOURCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON R
E
SIST
ANCE
V
GS
= 10V, I
D
= 12A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
Normalized Drain to Source On
Resistance vs Junction Temperature
Typical Characteristics
T
C
= 25C unless otherwise noted
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
6
Figure 11.
0.6
0.7
0.8
0.9
1.0
1.1
1.2
-80
-40
0
40
80
120
160
NORMA
L
I
Z
ED GA
TE
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250
A
THRESHOLD V
O
L
T
A
GE
Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12.
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN T
O
SOURCE
I
D
= 250
A
BREAKDO
WN V
O
L
T
A
GE
0.90
0.95
1.00
1.05
1.10
-80
-40
0
40
80
120
160
Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 13.
100
1000
0.1
1
10
60
40
6000
C, CAP
A
C
IT
ANCE (pF)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
=
C
GD
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Capacitance vs Drain to Source
Voltage
Figure 14.
0
2
4
6
8
10
0
5
10
15
20
25
30
35
V
GS
,
GA
TE T
O
SOURCE V
O
L
T
A
G
E
(V)
Q
g
, GATE CHARGE (nC)
V
DD
= 50V
I
D
= 12A
I
D
= 1A
WAVEFORMS IN
DESCENDING ORDER:
Gate Charge Waveforms for Constant
Gate Currents
Typical Characteristics
T
C
= 25C unless otherwise noted
Test Circuits and Waveforms
Figure 15.
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
Unclamped Energy Test Circuit
Figure 16.
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
Unclamped Energy Waveforms
Figure 17.
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
L
Gate Charge Test Circuit
Figure 18.
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
Q
gs2
Gate Charge Waveforms
Figure 19.
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
Switching Time Test Circuit
Figure 20.
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
Switching Time Waveforms
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
7
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
8
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application's ambient
temperature, T
A
(
o
C), and thermal resistance R
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(EQ. 1)
P
DM
T
JM
T
A
(
)
R
JA
-------------------------------
=
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part's current and maximum power
dissipation ratings. Precise determination of P
DM
is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer's preliminary application evaluation. Figure 21
defines the R
JA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
(EQ. 2)
R
JA
64
26
0.23
Area
+
-------------------------------
+
=
The transient thermal impedance (Z
JA
) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
100
150
200
0.001
0.01
0.1
1
10
50
Figure 21. Thermal Resistance vs Mounting
Pad Area
R
JA
= 64 + 26/(0.23+Area
)
R
JA
(
o
C/W)
AREA, TOP COPPER AREA (in
2
)
0
30
60
90
120
150
10
-1
10
0
10
1
10
2
10
3
Figure 22. Thermal Impedance vs Mounting Pad Area
t, RECTANGULAR PULSE DURATION (s)
Z
JA
, THERMAL
COPPER BOARD AREA - DESCENDING ORDER
0.04 in
2
0.28 in
2
0.52 in
2
0.76 in
2
1.00 in
2
I
M
P
ED
ANC
E (
o
C/W)
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
9
PSPICE Electrical Model
.SUBCKT FDS5672 2 1 3 ; rev June 2005
Ca 12 8 7e-10
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
Cb 15 14 7e-10
Cin 6 8 2.2e-10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 67
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 1.23e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 0.18e-9
RLgate 1 9 12.3
RLdrain 2 5 10
RLsource 3 7 1.8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1e-3
Rgate 9 20 1.4
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 3.2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),2.5))}
.MODEL DbodyMOD D (IS=4.5E-12 RS=4.7e-3 TRS1=1.5e-3 TRS2=2e-5
+ CJO=1.6e-9 M=0.55 TT=1.8e-8 XTI=3.0)
.MODEL DbreakMOD D (RS=2.5 TRS1=1.0e-3 TRS2=1e-6)
.MODEL DplcapMOD D (CJO=6.0e-10 IS=1.0e-30 N=10 M=0.45)
.MODEL MmedMOD NMOS (VTO=3.35 KP=4 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.4)
.MODEL MstroMOD NMOS (VTO=3.93 KP=50 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.82 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14 RS=0.1)
.MODEL RbreakMOD RES (TC1=7e-4 TC2=-1.3e-7)
.MODEL RdrainMOD RES (TC1=1.0e-4 TC2=1e-5)
.MODEL RSLCMOD RES (TC1=1.0e-2 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=1.0e-2 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.4e-5)
.MODEL RvtempMOD RES (TC1=-4e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-4.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=-0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
10
SABER Electrical Model
REV June 2005
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
ttemplate FDS5672 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=4.5e-12,rs=4.7e-3,trs1=1.5e-3,trs2=2e-5,cjo=1.6e-9,m=0.55,tt=1.8e-8,xti=3.0)
dp..model dbreakmod = (rs=2.5,trs1=1e-4,trs2=1e-6)
dp..model dplcapmod = (cjo=6.0e-10,isl=10.0e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=3.35,kp=4,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.93,kp=50,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.82,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-4.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0,voff=-0.5)
c.ca n12 n8 = 7e-10
c.cb n15 n14 = 7e-10
c.cin n6 n8 = 2.2e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 67
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 1.23e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 0.18e-9
res.rlgate n1 n9 = 12.3
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 1.8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=7e-4,tc2=-1.3e-7
res.rdrain n50 n16 = 1e-3, tc1=1e-4,tc2=1e-5
res.rgate n9 n20 = 1.4
res.rslc1 n5 n51 = 1e-6, tc1=1e-2,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.2e-3, tc1=1e-2,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-4e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5))
}
}
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
FDS5672
N-Channel PowerTrench
MOSFET
11
SPICE Thermal Model
REV June 2005
FDS5672_JA Junction Ambient
Copper Area = 1sq.in
CTHERM1 TH 8 2e-3
CTHERM2 8 7 5e-3
CTHERM3 7 6 1e-2
CTHERM4 6 5 4e-2
CTHERM5 5 4 9e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
SABER Thermal Model
SABER thermal model FDS5672
Copper Area = 1sq.in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2e-3
ctherm.ctherm2 8 7 =5e-3
ctherm.ctherm3 7 6 =1e-2
ctherm.ctherm4 6 5 =4e-2
ctherm.ctherm5 5 4 =9e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 =1
ctherm.ctherm8 2 tl =3
rrtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
7
JUNCTION
AMBIENT
8
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
T ABLE 1. THERMAL MODELS
COMPONANT
0.04 in
2
0.28 in
2
0.52 in
2
0.76 in
2
1.0 in
2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
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PRODUCT STATUS DEFINITIONS
Definition of Terms
ACExTM
ActiveArrayTM
BottomlessTM
CoolFETTM
CROSSVOLTTM
DOMETM
EcoSPARKTM
E
2
CMOSTM
EnSignaTM
FACTTM
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FASTrTM
FPSTM
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GlobalOptoisolatorTM
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HiSeCTM
I
2
CTM
i-Lo
TM
ImpliedDisconnect
TM
IntelliMAXTM
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LittleFETTM
MICROCOUPLERTM
MicroFETTM
MicroPakTM
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MSX
TM
MSXPro
TM
OCX
TM
OCXPro
TM
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OPTOPLANARTM
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PowerTrench
QFET
QSTM
QT OptoelectronicsTM
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RapidConfigure
TM
RapidConnect
TM
SerDes
TM
SILENT SWITCHER
SMART STARTTM
SPMTM
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SuperFETTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
SyncFETTM
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TruTranslationTM
UHCTM
UltraFET
UniFETTM
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Across the board. Around the world.
TM
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Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A
www.fairchildsemi.com
12
FDM3622 N-Channe
l P
o
w
e
rT
re
n
c
h
MOSFET
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