April 2005
FD
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2004 Fairchild Semiconductor Corporation
FDS8896 Rev. A1
www.fairchildsemi.com
1
FDS8896
N-Channel PowerTrench
MOSFET
30V, 15A, 6.0m
Features
r
DS(ON)
= 6.0m
, V
GS
= 10V, I
D
= 15A
r
DS(ON)
= 7.3m
, V
GS
= 4.5V, I
D
= 14A
High performance trench technology for extremely low
r
DS(ON)
Low gate charge
High power and current handling capability
Applications
DC/DC converters
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
r
DS(ON)
and fast switching speed.
SO-8
Branding Dash
1
5
2
3
4
4
3
2
1
5
6
7
8
FD
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FDS8896 Rev. A1
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2
MOSFET Maximum Ratings
T
A
= 25C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Electrical Characteristics
T
A
= 25C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Symbol
Parameter
Ratings
Units
V
DSS
Drain to Source Voltage
30
V
V
GS
Gate to Source Voltage
20
V
I
D
Drain Current
15
A
Continuous (T
A
= 25
o
C, V
GS
= 10V, R
JA
= 50
o
C/W)
Continuous (T
A
= 25
o
C, V
GS
= 4.5V, R
JA
= 50
o
C/W) 14
A
Pulsed
Figure 4
A
E
AS
Single Pulse Avalanche Energy (Note 1)
196
mJ
P
D
Power dissipation
2.5
W
Derate above 25
o
C
20
mW/
o
C
T
J
, T
STG
Operating and Storage Temperature
-55 to 150
o
C
R
JC
Thermal Resistance, Junction to Case (Note 2)
25
o
C/W
R
JA
Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)
50
o
C/W
R
JA
Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)
85
o
C/W
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDS8896
FDS8896
SO-8
330mm
12mm
2500 units
FDS8896
FDS8896_NL (Note 4)
SO-8
330mm
12mm
2500 units
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
B
VDSS
Drain to Source Breakdown Voltage
I
D
= 250
A, V
GS
= 0V
30
-
-
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24V
-
-
1
A
V
GS
= 0V
T
A
= 150
o
C
-
-
250
I
GSS
Gate to Source Leakage Current
V
GS
=
20V
-
-
100
nA
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
A
1.2
-
2.5
V
r
DS(ON)
Drain to Source On Resistance
I
D
= 15A, V
GS
= 10V
-
0.0049
0.0060
I
D
= 14A, V
GS
= 4.5V
-
0.0058
0.0073
I
D
= 15A, V
GS
= 10V,
T
A
= 150
o
C
-
0.0078
0.0101
C
ISS
Input Capacitance
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
-
2525
-
pF
C
OSS
Output Capacitance
-
490
-
pF
C
RSS
Reverse Transfer Capacitance
-
300
-
pF
R
G
Gate Resistance
V
GS
= 0.5V, f = 1MHz
0.6
2.4
4.2
Q
g(TOT)
Total Gate Charge at 10V
V
GS
= 0V to 10V
V
DD
= 15V
I
D
= 15A
I
g
= 1.0mA
-
50
67
nC
Q
g(5)
Total Gate Charge at 5V
V
GS
= 0V to 5V
-
28
36
nC
Q
g(TH)
Threshold Gate Charge
V
GS
= 0V to 1V
-
2.5
3.2
nC
Q
gs
Gate to Source Gate Charge
-
7.0
-
nC
Q
gs2
Gate Charge Threshold to Plateau
-
4.5
-
nC
Q
gd
Gate to Drain "Miller" Charge
-
11
-
nC
FD
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FDS8896 Rev. A1
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3
Switching Characteristics
(V
GS
= 10V)
Drain-Source Diode Characteristics
Notes:
1: Starting T
J
= 25C, L = 1mH, I
AS
= 19.8A, V
DD
= 30V, V
GS
= 10V.
2: R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. R
JC
is guaranteed by design while R
JA
is determined by the user's board design.
3: R
JA
is measured with 1.0 in
2
copper on FR-4 board
4: FDS8896_NL is lead free product. FDS8896_NL marking will appear on the reel label.
t
ON
Turn-On Time
V
DD
= 15V, I
D
= 14A
V
GS
= 10V, R
GS
= 6.2
-
-
68
ns
t
d(ON)
Turn-On Delay Time
-
8
-
ns
t
r
Rise Time
-
37
-
ns
t
d(OFF)
Turn-Off Delay Time
-
60
-
ns
t
f
Fall Time
-
24
-
ns
t
OFF
Turn-Off Time
-
-
126
ns
V
SD
Source to Drain Diode Voltage
I
SD
= 15A
-
-
1.25
V
I
SD
= 2.1A
-
-
1.0
V
t
rr
Reverse Recovery Time
I
SD
= 15A, dI
SD
/dt = 100A/
s
-
-
29
ns
Q
RR
Reverse Recovered Charge
I
SD
= 15A, dI
SD
/dt = 100A/
s
-
-
15
nC
FD
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FDS8896 Rev. A1
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4
Typical Characteristics
T
A
= 25C unless otherwise noted
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
T
A
, AMBIENT TEMPERATURE (
o
C)
PO
WE
R
D
I
SSI
P
A
T
I
O
N
M
U
L
T
I
P
L
I
ER
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
0
5
10
15
20
I
D
,
DR
AI
N
C
URRE
NT
(
A
)
T
A
, AMBIENT TEMPERATURE (
o
C)
R
JA
=50
o
C/W
V
GS
= 10V
V
GS
= 4.5V
25
50
75
100
125
150
0.001
0.01
0.1
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
2
t, RECTANGULAR PULSE DURATION (s)
Z
JA
, NO
RM
AL
IZ
E
D
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JA
x R
JA
+ T
A
P
DM
t
1
t
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
T
H
E
R
M
A
L
IM
P
E
D
ANCE
R
JA
=50
o
C/W
10
100
1000
2000
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
I
DM
,
P
E
AK CURRE
NT
(
A
)
t , PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
GS
= 10V
T
A
= 25
o
C
I = I
25
175 - T
A
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 4.5V
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FDS8896 Rev. A1
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5
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Unclamped Inductive Switching
Capability
Figure 6. Transfer Characteristics
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
Typical Characteristics
T
A
= 25C unless otherwise noted
1
10
100
0.1
1
10
100
I
AS
, A
V
AL
ANCHE
C
URRE
NT
(
A
)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0
10
20
30
40
50
1.5
2.0
2.5
3.0
3.5
I
D
, DRAIN CURRE
NT
(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= 25
o
C
T
J
= -55
o
C
0
10
20
30
40
50
0
0.1
0.2
0.3
0.4
0.5
I
D
, DRAIN CURRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
GS
= 3V
V
GS
= 10V
T
A
= 25
o
C
V
GS
= 5V
V
GS
= 2.5V
V
GS
= 4V
4
6
8
10
12
14
2
4
6
8
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 15A
r
DS
(
O
N)
, DRAIN T
O
S
O
U
RCE
O
N
RE
S
I
S
T
ANCE
(
m
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0.6
0.8
1.0
1.2
1.4
1.6
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
T
J
, JUNCTION TEMPERATURE (
o
C)
O
N
RE
S
I
S
T
ANCE
V
GS
= 10V, I
D
= 15A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
-80
-40
0
40
80
120
160
0.6
1.0
1.2
NO
RM
AL
IZ
E
D
G
A
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250
A
T
HRE
S
H
O
L
D V
O
L
T
A
G
E
-80
-40
0
40
80
120
160
0.8
FD
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FDS8896 Rev. A1
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6
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
Figure 13. Gate Charge Waveforms for Constant Gate Currents
Typical Characteristics
T
A
= 25C unless otherwise noted
0.90
0.95
1.00
1.05
1.10
T
J
, JUNCTION TEMPERATURE (
o
C)
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
I
D
= 250
A
BRE
AKDO
W
N
V
O
L
T
A
G
E
-80
-40
0
40
80
120
160
100
1000
0.1
1
10
30
5000
C
,
CAP
A
C
IT
ANCE
(
p
F
)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
=
C
GD
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0
2
4
6
8
10
0
10
20
30
40
50
V
GS
, G
A
T
E
T
O
S
O
URCE
V
O
L
T
A
G
E
(
V
)
Q
g
, GATE CHARGE (nC)
V
DD
= 15V
I
D
= 15A
I
D
= 1A
WAVEFORMS IN
DESCENDING ORDER:
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FDS8896 Rev. A1
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7
Test Circuits and Waveforms
Figure 14. Unclamped Energy Test Circuit
Figure 15. Unclamped Energy Waveforms
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
Figure 18. Switching Time Test Circuit
Figure 19. Switching Time Waveforms
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
L
V
DD
Q
g(TH)
V
GS
= 1V
Q
gs2
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
Q
g(5)
V
GS
= 5V
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
FD
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FDS8896 Rev. A1
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8
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application's ambient
temperature, T
A
(
o
C), and thermal resistance R
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part's current and maximum power
dissipation ratings. Precise determination of P
DM
is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer's preliminary application evaluation. Figure 21
defines the R
JA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
The transient thermal impedance (Z
JA
) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
(EQ. 1)
P
DM
T
JM
T
A
(
)
R
JA
-------------------------------
=
(EQ. 2)
R
JA
64
26
0.23
Area
+
-------------------------------
+
=
100
150
200
0.001
0.01
0.1
1
10
50
Figure 21. Thermal Resistance vs Mounting
Pad Area
R
JA
= 64 + 26/(0.23+Area)
R
JA
(
o
C/W
)
AREA, TOP COPPER AREA (in
2
)
0
30
60
90
120
150
10
-1
10
0
10
1
10
2
10
3
Figure 22. Thermal Impedance vs Mounting Pad Area
t, RECTANGULAR PULSE DURATION (s)
Z
JA
, T
H
E
R
MAL
COPPER BOARD AREA - DESCENDING ORDER
0.04 in
2
0.28 in
2
0.52 in
2
0.76 in
2
1.00 in
2
IM
P
E
D
ANCE
(
o
C/W
)
FD
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FDS8896 Rev. A1
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9
PSPICE Electrical Model
.SUBCKT FDS8896 2 1 3 ;
rev February 2004
Ca 12 8 1.8e-9
Cb 15 14 1.8e-9
Cin 6 8 2.2e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 33.1
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 1.5e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1e-9
RLgate 1 9 15
RLdrain 2 5 10
RLsource 3 7 10
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.52e-3
Rgate 9 20 2.4
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}
.MODEL DbodyMOD D (IS=4E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=8.8e-10 M=0.57 TT=1e-12 XTI=2.2)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=9e-10 IS=1e-30 N=10 M=0.39)
.MODEL MmedMOD NMOS (VTO=1.98 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.4)
.MODEL MstroMOD NMOS (VTO=2.4 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.63 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=24 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-1e-6)
.MODEL RdrainMOD RES (TC1=1e-4 TC2=8e-6)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=7e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1.3e-3 TC2=-7e-6)
.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
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+
-
+
-
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FDS8896 Rev. A1
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10
SABER Electrical Model
REV February 2004
template FDS8896 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=4e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-12,xti=2.2)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=9e-10,isl=10e-30,nl=10,m=0.39)
m..model mmedmod = (type=_n,vto=1.98,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.4,kp=350,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.63,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2)
c.ca n12 n8 = 1.8e-9
c.cb n15 n14 = 1.8e-9
c.cin n6 n8 = 2.2e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 33.1
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 1.5e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1e-9
res.rlgate n1 n9 = 15
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 10
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-1e-6
res.rdrain n50 n16 = 2.52e-3, tc1=1e-4,tc2=8e-6
res.rgate n9 n20 = 2.4
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2e-3, tc1=7e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-1.3e-3,tc2=-7e-6
res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
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+
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+
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FDS8896 Rev. A1
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11
SPICE Thermal Model
REV February 2004
FDS8896T
Copper Area =1.0 in
2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
SABER Thermal Model
Copper Area = 1.0 in
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
7
JUNCTION
CASE
8
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
TABLE 1. THERMAL MODELS
COMPONANT
0.04 in
2
0.28 in
2
0.52 in
2
0.76 in
2
1.0 in
2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
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intended to be an exhaustive list of all such trademarks.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
ACExTM
ActiveArrayTM
BottomlessTM
CoolFETTM
CROSSVOLTTM
DOMETM
EcoSPARKTM
E
2
CMOSTM
EnSignaTM
FACTTM
FACT Quiet SeriesTM
FAST
FASTrTM
FPSTM
FRFETTM
GlobalOptoisolatorTM
GTOTM
HiSeCTM
I
2
CTM
i-LoTM
ImpliedDisconnectTM
IntelliMAXTM
ISOPLANARTM
LittleFETTM
MICROCOUPLERTM
MicroFETTM
MicroPakTM
MICROWIRETM
MSXTM
MSXProTM
OCXTM
OCXProTM
OPTOLOGIC
OPTOPLANARTM
PACMANTM
POPTM
Power247TM
PowerEdgeTM
PowerSaverTM
PowerTrench
QFET
QSTM
QT OptoelectronicsTM
Quiet SeriesTM
RapidConfigureTM
RapidConnectTM
SerDesTM
SILENT SWITCHER
SMART STARTTM
SPMTM
StealthTM
SuperFETTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
SyncFETTM
TinyLogic
TINYOPTOTM
TruTranslationTM
UHCTM
UltraFET
UniFETTM
VCXTM
Across the board. Around the world.TM
The Power Franchise
Programmable Active DroopTM
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
FDS8896 Rev. A
www.fairchildsemi.com
12
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