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Электронный компонент: FDS9936A

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May 1998

FDS9936A
Dual N-Channel Enhancement Mode Field Effect Transistor

General Description
Features
Absolute Maximum Ratings
T
A
= 25
o
C unless other wise noted
Symbol
Parameter
FDS9936A
Units
V
DSS
Drain-Source Voltage
30
V
V
GSS
Gate-Source Voltage
20
V
I
D
Drain Current - Continuous
(Note 1a)
5.5
A
- Pulsed
20
P
D
Power Dissipation for Dual Operation
2
W
Power Dissipation for Single Operation
(Note 1a)
1.6
(Note 1b)
1
(Note 1c)
0.9
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
40
C/W
FDS9936A Rev.B
5.5 A, 30 V. R
DS(ON)
= 0.040
@ V
GS
= 10 V,
R
DS(ON)
= 0.060
@ V
GS
= 4.5 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely
used surface mount package.
Dual MOSFET in surface mount package
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to provide superior switching
performance and minimize on-state resistance. These devices
are particularly suited for low voltage applications such as disk
drive motor control, battery powered circuits where fast
switching, low in-line power loss, and resistance to transients
are needed.
S1
D1
S2
G1
SO-8
D2
D2
D1
G2
FDS
9936A
pin
1
1
5
7
8
2
3
4
6
1998 Fairchild Semiconductor Corporation
Electrical Characteristics (
T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 A
30
V
BV
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
I
D
= 250 A, Referenced to 25
o
C
32
mV/
o
C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
1
A
T
J
= 55C
10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 20 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -20 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 A
1
1.5
3
V
V
GS(th)
/
T
J
Gate Threshold Voltage Temp. Coefficient
I
D
= 250 A, Referenced to 25
o
C
-4.3
mV/
o
C
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 5.5 A
0.03
0.04
T
J
=125C
0.046
0.068
V
GS
= 4.5 V, I
D
= 4.5 A
0.045
0.06
I
D(ON)
On-State Drain Current
V
GS
= 10 V, V
DS
= 5 V
20
A
g
FS
Forward Transconductance
V
DS
= 5 V, I
D
= 4.7 A
7
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
350
pF
C
oss
Output Capacitance
220
pF
C
rss
Reverse Transfer Capacitance
80
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= 10 V, I
D
= 1 A,
7.5
15
ns
t
r
Turn - On Rise Time
V
GS
= 4.5 V, R
GEN
= 6
12
25
t
D(off)
Turn - Off Delay Time
13
25
t
f
Turn - Off Fall Time
6
15
Q
g
Total Gate Charge
V
DS
= 15 V, I
D
= 5 A,
12
17
nC
Q
gs
Gate-Source Charge
V
GS
= 10 V
2.1
Q
gd
Gate-Drain Charge
2.6
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
1.3
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.3 A
(Note 2)
0.76
1.2
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
FDS9936A Rev.B
c. 135
O
C/W on a 0.003 in
2
pad of 2oz copper.
b. 125
O
C/W on a 0.02 in
2
pad of 2oz copper.
a. 78
O
C/W on a 0.5 in
2
pad of 2oz copper.
FDS9936A Rev.B
0
0.5
1
1.5
2
2.5
3
0
4
8
12
16
20
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
DS
D
3.5V
3.0V
4.0V
V = 10V
GS
5.5V
4.5V
0
5
10
15
20
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 3.5V
GS
D
R , NORMALIZED
DS(ON)
10V
4.5 V
6.0V
5.0V
4.0 V
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
-50
-25
0
25
50
75
100
125
150
0.6
0.8
1
1.2
1.4
1.6
1.8
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
R , NORMALIZED
DS(ON)
V = 10V
GS
I = 5.5A
D
Figure 3. On-Resistance Variation with
Temperature.
1
2
3
4
5
0
3
6
9
12
15
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V =5.0V
DS
GS
D
T = -55C
J
125C
25C
Figure 5. Transfer Characteristics.
0
0.2
0.4
0.6
0.8
1
1.2
0.0001
0.001
0.01
0.1
1
10
40
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
25C
-55C
V = 0V
GS
SD
S
T = 125C
J
Figure 6 . Body Diode Forward Voltage
Variation with Source Current
and Temperature.
2
4
6
8
10
0
0.05
0.1
0.15
0.2
V , GATE TO SOURCE VOLTAGE (V)
GS
R , ON-RESISTANCE (OHM)
DS(ON)
25C
I = 3A
D
T = 125C
J
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
FDS9936A Rev.B
0
2
4
6
8
10
12
14
0
2
4
6
8
10
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 5.5A
D
V = 5V
DS
10V
15V
0.1
0.2
0.5
1
2
5
10
30
50
0.01
0.05
0.1
0.5
1
2
5
10
30
50
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
RDS(ON) LIMIT
D
A
DC
DS
1s
100ms
10ms
1ms
10s
V =10V
SINGLE PULSE
R = 135C/W
T = 25C
JA
GS
A
100us
Figure 10. Single Pulse Maximum Power
Dissipation.
0.1
0.2
0.5
1
2
5
10
30
30
50
100
200
500
1000
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
C
iss
f = 1 MHz
V = 0 V
GS
C
oss
C
rss
DS
Figure 8. Capacitance Characteristics.
Figure 7. Gate Charge Characteristics.
Figure 9. Maximum Safe Operating Area.
Typical Electrical Characteristics
(continued)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
0.01
0.1
0.5
1
10
50 100
300
0
5
10
15
20
25
30
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =135 C/W
T = 25C
JA
A
0.0001
0.001
0.01
0.1
1
10
100
300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t /t
1 2
R (t) = r(t) * R
R =135 C/W
JA
JA
JA
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
SOIC(8lds) Packaging
Configuration:
Figure 1.0
Components
Leader Tape
1680mm minimum or
210 empty pockets
Trailer Tape
640mm minimum or
80 empty pockets
SOIC(8lds) Tape Leader and Trailer
Configuration:
Figure 2.0
Cover Tape
Carrier Tape
Note/Comments
Packaging Option
SOIC (8lds) Packaging Information
Standard
(no flow code)
L86Z
F011
Packaging type
Reel Size
TNR
13" Dia
Rail/Tube
-
TNR
13" Dia
Qty per Reel/Tube/Bag
2,500
95
4,000
Box Dimension (mm)
343x64x343
530x130x83
343x64x343
Max qty per Box
5,000
30,000
8,000
D84Z
TNR
7" Dia
500
184x187x47
1,000
Weight per unit (gm)
0.0774
0.0774
0.0774
0.0774
Weight per Reel (kg)
0.6060
-
0.9696
0.1182
F63TN Label
ESD Label
343mm x 342mm x 64mm
Standard Intermediate box
ESD Label
F63TNR Label sample
F63TNLabel
LOT: CBVK741B019
FSID: FDS9953A
D/C1: D9842 QTY1:
SPEC REV:
SPEC:
QTY: 2500
D/C2:
QTY2:
CPN:
N/F: F (F63TNR)3
F852
NDS
9959
SOIC-8 Unit Orientation
F
85
2
NDS
99
59
Pin 1
Static Dissipative
Embossed Carrier Tape
F63TNR
Label
Antistatic Cover Tape
ESD Label
EL ECT RO ST AT IC
SEN SIT IVE DEVI CES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC
EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
TNR D ATE
PT NUMB ER
PEEL STREN GTH MIN ___ __ ____ __ ___gms
MAX ___ ___ ___ ___ _ gms
Customized
Label
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
F
85
2
NDS
99
59
F
85
2
NDS
99
59
F
85
2
NDS
99
59
SO-8 Tape and Reel Data and Package Dimensions
July 1999, Rev. B
1998 Fairchild Semiconductor Corporation
Dimensions are in millimeter
Pkg type
A0
B0
W
D0
D1
E1
E2
F
P1
P0
K0
T
Wc
Tc
SOIC(8lds)
(12mm)
6.50
+/-0.10
5.30
+/-0.10
12.0
+/-0.3
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
10.25
min
5.50
+/-0.05
8.0
+/-0.1
4.0
+/-0.1
2.1
+/-0.10
0.450
+/-
0.150
9.2
+/-0.3
0.06
+/-0.02
P1
A0
D1
P0
F
W
E1
D0
E2
B0
Tc
Wc
K0
T
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
12mm
7" Dia
7.00
177.8
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
12mm
13" Dia
13.00
330
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
7.00
178
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Option
Dim A
Max
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim D
min
Dim C
B Min
DETAIL AA
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum component rotation
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
Typical
component
cavity
center line
20 deg maximum
Typical
component
center line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or Front Sectional View)
Component Rotation
User Direction of Feed
SOIC(8lds) Embossed Carrier Tape
Configuration:
Figure 3.0
SOIC(8lds) Reel Configuration: Figure 4.0
SO-8 Tape and Reel Data and Package Dimensions, continued
July 1999, Rev. B
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
SO-8 Tape and Reel Data and Package Dimensions, continued
September 1998, Rev. A
9
TRADEMARKS
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CROSSVOLTTM
E
2
CMOS
TM
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FAST
FASTrTM
GTOTM
HiSeCTM
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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