2001 Fairchild Semiconductor Corporation
DS500508
www.fairchildsemi.com
August 2001
Revised December 2001
FI
N1032
3.
3V L
V
DS 4-
Bit
Hi
gh Spe
e
d Di
ff
erent
i
al
R
e
ceiver
FIN1032
3.3V LVDS 4-Bit High Speed Differential Receiver
General Description
This quad receiver is designed for high speed interconnect
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
The FIN1032 can be paired with its companion driver, the
FIN1031, or any other Fairchild LVDS driver.
Features
s
Greater than 400Mbs data rate
s
3.3V power supply operation
s
0.4ns maximum differential pulse skew
s
2.5ns maximum propagation delay
s
Low power dissipation
s
Power OFF protection
s
Fail safe protection for open-circuit, shorted and termi-
nated conditions
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
Pin compatible with equivalent RS-422 and LVPECL
devices
s
16-Lead SOIC and TSSOP packages save space
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don't Care
Z
=
High Impedance
Fail Safe
=
Open, Shorted, Terminated
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
FIN1032M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1032MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Inputs
Outputs
EN
EN
R
IN
+
R
OUT
-
R
OUT
H
X
H
L
H
H
X
L
H
L
H
X
Fail Safe Condition
H
X
L
H
L
H
X
L
L
H
L
X
L
Fail Safe Condition
H
L
H
X
Z
Pin Name
Description
R
OUT1
, R
OUT2
, R
OUT3
, R
OUT4
LVTTL Data Outputs
R
IN1
+
, R
IN2
+
, R
IN3
+
, R
IN4
+
Non-Inverting LVDS Inputs
R
IN1
-
, R
IN2
-
, R
IN3
-
, R
IN4
-
Inverting LVDS Inputs
EN
Driver Enable Pin
EN
Inverting Driver Enable Pin
V
CC
Power Supply
GND
Ground
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2
FIN1032
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings": are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 2: All typical values are at T
A
=
25
C and with V
CC
=
3.3V.
Supply Voltage (V
CC
)
-
0.5V to
+
4.6 V
DC Input Voltage (V
IN
)
-
0.5V to
+
4.6 V
DC Input Voltage (V
OUT
)
-
0.5V to 6 V
DC Output Current (I
O
)
16 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Max Junction Temperature (T
J
)
150
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
ESD (Human Body Model)
10,000 V
ESD (Machine Model)
500 V
Supply Voltage (V
CC
)
3.0 V to 3.6 V
Magnitude of Differential Voltage
(|V
ID
|)
100 mV to V
CC
Common-Mode Input Voltage (V
IC
)
0.05 V to 2.35V
Input Voltage (V
IN
)
0 to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 2)
V
TH
Differential Input Threshold HIGH
See Figure 1 and Table 1
100
mV
V
TL
Differential Input Threshold LOW
See Figure 1 and Table 1
-
100
mV
I
IN
Input Current
V
IN
=
0V or V
CC
20
A
I
I(OFF)
Power-OFF Input Current
V
CC
=
0V, V
IN
=
0V or 3.6V
20
A
V
IH
Input High Voltage (EN or EN)
2.0
V
CC
V
V
IL
Input Low Voltage (EN or EN)
GND
0.8
V
V
OH
Output HIGH Voltage
I
OH
=
-
100
A
V
CC
-
0.2
V
I
OH
=
-
8 mA
2.4
V
OL
Output LOW Voltage
I
OH
=
100
A
0.2
V
I
OL
=
8 mA
0.5
V
IK
Input Clamp Voltage
I
IK
=
-
18 mA
-
1.5
V
I
OZ
Disabled Output Leakage Current
EN
=
0.8 and EN
=
2V, V
OUT
=
3.6V or 0V
20
A
I
OS
Output Short Circuit Test
Receiver Enabled, V
OUT
=
0V
-
15
-
100
mA
(one output shorted at a time)
I
CCZ
Disabled Power Supply Current
Receiver Disabled
5
mA
I
CC
Power Supply Current
Receiver Enabled, (R
IN
+
=
1V and R
IN
-
=
1.4V)
15
mA
or (R
IN
+
=
1.4V and R
IN
-
=
1V)
I
PU/PD
Output Power Up/Power Down
V
CC
=
0V to 1.5V
20
A
High Z Leakage Current
C
IN
Input Capacitance
3.5
pF
C
OUT
Output Capacitance
6
pF
3
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FI
N1032
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3: All typical values are at T
A
=
25
C and with V
CC
=
3.3V.
Note 4: t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5: t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: f
MAX
Criteria: Input t
R
= t
F
<
1 ns, V
ID
=
300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, V
OL
<
0.5V, V
OH
>
2.4V.
All channels switching in phase.
Note A: All input pulses have frequency
=
10MHz, t
R
or t
F
=
1ns
Note B: C
L
includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 3)
t
PLH
Propagation Delay LOW-to-HIGH
1.0
2.5
ns
t
PHL
Propagation Delay HIGH-to-LOW
1.0
2.5
ns
t
TLH
Output Rise Time (20% to 80%)
|V
ID
|
=
400 mV, C
L
=
10 pF,
0.7
1.2
ns
t
THL
Output Fall Time (80% to 20%)
R
L
=
1k
0.7
1.2
ns
t
SK(P)
Pulse Skew |t
PLH
- t
PHL
|
See Figure 1 and Figure 2
0.4
ns
t
SK(LH)
Channel-to-Channel Skew
0.3
ns
t
SK(HL)
(Note 4)
t
SK(PP)
Part-to-Part Skew (Note 5)
1.0
ns
f
MAX
Maximum Operating Frequency
R
L
=
1k
, C
L
=
10 pF,
200
325
MHz
(Note 6)
see Figure 1 and Figure 2
t
ZH
LVTTL Output Enable Time from Z to HIGH
5.0
ns
t
ZL
LVTTL Output Enable Time from Z to LOW
R
L
=
1k
, C
L
=
10 pF,
5.0
ns
t
HZ
LVTTL Output Disable Time from HIGH to Z
See Figure 3 and Figure 4
5.0
ns
t
LZ
LVTTL Output Disable Time from LOW to Z
5.0
ns
Applied Voltages (V)
Resulting Differential Input
Resulting Common Mode Input
Voltage (mA)
Voltage (V)
V
IA
V
IB
V
ID
V
IC
1.25
1.15
100
1.2
1.15
1.25
-
100
1.2
2.4
2.3
100
2.35
2.3
2.4
-
100
2.35
0.1
0
100
0.05
0
0.1
-
100
0.05
1.5
0.9
600
1.2
0.9
1.5
-
600
1.2
2.4
1.8
600
2.1
1.8
2.4
-
600
2.1
0.6
0
600
0.3
0
0.6
-
600
0.3
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4
FIN1032
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
FIGURE 3. AC Loading Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
Note A: C
L
includes probes and jig capacitance
Note B: All LVTTL input pulses have the following characteristics: Frequency
=
10 MHz t
R
or t
F
2 ns
FIGURE 4. LVTTL Outputs Test Circuit and AC Waveforms
5
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FI
N1032
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
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