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Preliminary
2005 Fairchild Semiconductor Corporation
DS500888
www.fairchildsemi.com
April 2005
Revised May 2005
FI
N24A
P
SerDes Low
V
o
l
t
age
2
4
-Bi
t
Bi-
D
ire
c
ti
onal Seri
al
ize
r
/Des
eri
a
li
zer wit
h
Mul
t
i
p
le
Fr
equency Ranges
(
P
rel
i
mi
nary)
FIN24A
P
SerDes
Low Voltage 24-Bit Bi-Directional Serializer/Deserializer
with Multiple Frequency Ranges (Preliminary)
General Description
The FIN24A allows for a pair of SerDes to interleave data
from two different data sources going opposite directions or
standard bi-directional interface operation. The bi-direc-
tional data flow is controlled through use of a direction
(DIRI) control pin. The devices can be configured to oper-
ate in a unidirectional mode only by hardwiring the DIRI
pin. An internal PLL generates the required bit clock fre-
quency for transfer across the serial link. The FIN24A sup-
ports multiple input frequency ranges which are selected
by the S1 and S2 control pins. Options exist for dual or sin-
gle PLL operation dependent upon system operational
parameters. The device has been designed for low power
operation and utilizes Fairchild Low Power LVDS interface.
The device also supports an ultra low power Power-Down
mode for conserving power in battery operated applica-
tions.
Features
s
Low power consumption
s
Low power standards based LVDS differential interface
s
LVCMOS parallel I/O interface
2 mA source/sink current
Over-voltage tolerant control signals
s
I/O Power Supply range between 1.65V and 3.6V
s
Analog Power Supply range of 2.775V
r
5%
s
Multi-Mode operation allows for a single device to
operate as Serializer or Deserializer
s
Internal PLL with no external components
s
Standby Power-Down mode support
s
Small footprint 40-terminal MLP packaging
s
Built in differential termination
s
Supports external CKREF frequencies between 2MHz
and 30MHz
s
Serialized data rate up to 780Mb/s
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
BGX and MLP packages available in Tape and Reel only.
P
SerDes
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
FIN24AGFX
(Preliminary)
BGA042A
Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195,
3.5mm Wide
FIN24AMLX
MLP040A
Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm
Square
Preliminary
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Functional Block Diagram
Connection Diagram
Terminal Assignments for MLP
(Top View)
Preliminary
3
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FI
N24A
Terminal Description
Note 1: The DSO/DSI serial port pins have been arranged such that when one device is rotated 180 degrees with respect to the other device the serial con-
nections will properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross.
Control Logic Circuitry
The FIN24A has the ability to be used as a 24-bit Serializer
or a 24-bit Deserializer. Pins S1 and S2 must be set to
accommodate the clock reference input frequency range of
the serializer. The table below shows the pin programming
of these options based on the S1 and S2 control pins. The
DIRI pin controls whether the device is a serializer or a
deserializer. When DIRI is asserted LOW, the device is
configured as a deserializer. When the DIRI pin is asserted
HIGH, the device will be configured as a serializer. Chang-
ing the state on the DIRI signal will reverse the direction of
the I/O signals and generate the opposite state signal on
DIRO. For unidirectional operation the DIRI pin should be
hardwired to the HIGH or LOW state and the DIRO pin
should be left floating. For bi-directional operation the DIRI
of the master device will be driven by the system and the
DIRO signal of the master will be used to drive the DIRI of
the slave device.
Serializer/Deserializer
with Dedicated I/O Variation
The serialization and deserialization circuitry is setup for 24
bits. Because of the dedicated inputs and outputs only 22
bits of data are ever serialized or deserialized. Regardless
of the mode of operation the serializer is always sending 24
bits of data plus 2 boundary bits and the deserializer is
always receiving 24 bits of data and 2 word boundary bits.
Bits 23 and 24 of the serializer will always contain the value
of zero and will be discarded by the deserializer. DP[21:22]
input to the serializer will be deserialized to DP[23:24]
respectively.
Turn-Around Functionality
The device passes and inverts the DIRI signal through the
device asynchronously to the DIRO signal. Care must be
taken by the system designer to insure that no contention
occurs between the deserializer outputs and the other
devices on this port. Optimally the peripheral device driving
the serializer should be put into a HIGH Impedance state
prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer the dedicated outputs will remain
at the last logical value asserted. This value will only
change if the device is once again turned around into a
deserializer and the values are overwritten.
Terminal Name
I/O Type
Number
of
Terminals
Description of Signals
DP[1:20]
I/O
20
LVCMOS Parallel I/O. Direction controlled by DIRI pin
DP[21:22]
I
2
LVCMOS Parallel Unidirectional Inputs
DP[23:24]
O
2
LVCMOS Unidirectional Parallel Outputs
CKREF
IN
1
LVCMOS Clock Input and PLL Reference
STROBE
IN
1
LVCMOS Strobe Signal for Latching Data into the Serializer
CKP
OUT
1
LVCMOS Word Clock Output
DSO
/ DSI
DSO
/ DSI
DIFF-I/O
2
LpLVDS Differential Serial I/O Data Signals (Note 1)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)
: Positive signal of DSO(I) pair
DSO(I)
: Negative signal of DSO(I) pair
CKSI
, SKSI
DIFF-IN
2
LpLVDS Differential Deserializer Input Bit Clock
CKSI: Refers to signal pair
CKSI
: Positive signal of CKSI pair
CKSI
: Negative signal of CKSI pair
CKSO
, SKSO
DIFF-OUT
2
LpLVDS Differential Serializer Output Bit Clock
CKSO: Refers to signal pair
CKSO
: Positive signal of CKSO pair
CKSO
: Negative signal of CKSO pair
S1
IN
1
LVCMOS Mode Selection terminals used to select
S2
IN
1
Frequency Range for the RefClock, CKREF
DIRI
IN
1
LVCMOS Control Input
Used to control direction of Data Flow:
DIRI
"1" Serializer, DIRI
"0" Deserializer
DIRO
OUT
1
LVCMOS Control Output
Inversion of DIRI
V
DDP
Supply
1
Power Supply for Parallel I/O and Translation Circuitry
V
DDS
Supply
1
Power Supply for Core and Serial I/O
V
DDA
Supply
1
Power Supply for Analog PLL Circuitry
GND
Supply
0
Use Bottom Ground Plane for Ground Signals
Preliminary
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TABLE 1. Control Logic Circuitry
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state the PLL and references will be disabled, differ-
ential input buffers will be shut off, differential output buffers
will be placed into a HIGH impedance state, LVCMOS out-
puts will be placed into a HIGH impedance state and
LVCMOS inputs will be driven to a valid level internally.
Additionally all internal circuitry will be reset. The loss of
CKREF state is also enabled to insure that the PLL will only
power-up if there is a valid CKREF signal.
In a typical application mode signals of the device will typi-
cally not change states other than between the desired fre-
quency range and the power-down mode. This allows for
system level power-down functionality to be implemented
via a single wire for a SerDes pair. The S1 and S2 selection
signals that have their operating mode driven to a "logic 0"
should be hardwired to GND. The S1 and S2 signals that
have their operating mode driven to a "logic 1" should be
connected to a system level power-down signal.
Serializer Operation Mode
The serializer configurations are described in the following
sections. The basic serialization circuitry works essentially
identical in these modes but the actual data and clock
streams will differ dependent on if CKREF is the same as
the STROBE signal or not. When it is stated that
CKREF
STROBE this means that the CKREF and
STROBE signals have an identical frequency of operation
but may or may not be phase aligned. When it is stated that
CKREF does not equal STROBE then each signal is dis-
tinct and CKREF must be running at a frequency high
enough to avoid any loss of data condition. CKREF must
never be a lower frequency than STROBE.
Serializer Operation: (Figure 1)
Modes 1, 2, or 3
DIRI equals 1
CKREF equals STROBE
The PLL must receive a stable CKREF signal in order to
achieve lock prior to any valid data being sent. The CKREF
signal can be used as the data STROBE signal provided
that data can be ignored during the PLL lock phase.
Once the PLL is stable and locked the device can begin to
capture and serialize data. Data will be captured on the ris-
ing edge of the STROBE signal and then serialized. The
serialized data stream is synchronized and sent source
synchronously with a bit clock with an embedded word
boundary. When operating in this mode the internal deseri-
alizer circuitry is disabled including the serial clock, serial
data input buffers, the bi-directional parallel outputs and the
CKP word clock. The CKP word clock will be driven HIGH.
Serializer Operation: (Figure 2)
DIRI equals 1
CKREF does not equal STROBE
If the same signal is not used for CKREF and STROBE,
then the CKREF signal must be run at a higher frequency
than the STROBE rate in order to serialize the data cor-
rectly. The actual serial transfer rate will remain at 26 times
the CKREF frequency. A data bit value of zero will be sent
when no valid data is present in the serial bit stream. The
operation of the serializer will otherwise remain the same.
The exact frequency that the reference clock needs to run
at will be dependent upon the stability of the CKREF and
STROBE signal. If the source of the CKREF signal imple-
ments spread spectrum technology then the maximum fre-
quency of this spread spectrum clock should be used in
calculating the ratio of STROBE frequency to the CKREF
frequency. Similarly if the STROBE signal has significant
cycle-to-cycle variation then the maximum cycle-to-cycle
time needs to be factored into the selection of the CKREF
frequency.
Serializer Operation: (Figure 3)
DIRI equals 1
No CKREF
A third method of serialization can be done by providing a
free running bit clock on the CKSI signal. This mode is
enabled by grounding the CKREF signal and driving the
DIRI signal HIGH.
At power-up the device is configured to accept a serializa-
tion clock from CKSI. If a CKREF is received then this
device will enable the CKREF serialization mode. The
device will remain in this mode even if CKREF is stopped.
To re-enable this mode the device must be powered down
and then powered back up with a "logic 0" on CKREF.
Mode
Number
S2 S1 DIRI
Description
0
0
0
x
Power-Down Mode
1
0
1
1
24-Bit Serializer
2MHz to 5MHz CKREF
0
1
0
24-Bit Deserializer
2
1
0
1
24-Bit Serializer
5MHz to 15MHz CKREF
1
0
0
24-Bit Deserializer
3
1
1
1
24-Bit Serializer
10MHz to 30MHz CKREF
1
1
0
24-Bit Deserializer
Preliminary
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FI
N24A
Serializer Operation Mode
(Continued)
FIGURE 1. Serializer Timing Diagram (CKREF equals STROBE)
FIGURE 2. Serializer Timing Diagram (CKREF does not equal STROBE)
FIGURE 3. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)
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