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FM24C256 rev. B.3

FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

June 2000

FM24C256
256 KBit 2-Wire Bus Interface
Serial EEPROM with Write Protect

General Description

The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS
nonvolatile electrically erasable memory. These devices offer the
designer different low voltage and low power options. They
conform to all requirements in the Extended IIC 2-wire protocol.
Furthermore, they are designed to minimize device pin count and
simplify PC board layout requirements.

The entire memory array can be write disabled (Write Protection)
by connecting the WP pin to V

Functional address lines allow up to eight devices on the same
bus, for up to a total of 2 Mbit address space.

The IIC communication protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).

Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption.

Block Diagram

Features

I Extended Operating Voltages

-- C256: 4.5V - 5.5V
-- C256L: 2.7V - 5.5V
-- C256LZ: 2.7V - 5.5V

I Low Power CMOS

-- 1mA active current typical
-- C256/C256L: 10

µA standby current typical

-- C256LZ: less than 1

µA standby current

I 2-wire IIC serial interface
I 64 byte page write mode
I Max write cycle time of 6ms byte/page
I 40 years data retention
I Endurance: 100,000 data changes
I Hardware write protect for entire array
I Schmitt trigger inputs for noise suppression
I Electrostatic discharge protection > 4000V
I 8-pin DIP and 8-pin SO (150 mil) packages. Contact factory

for CSP package availability

DS800023-1

H.V. GENERATION

TIMING &CONTROL

E2PROM

ARRAY

YDEC

DATA REGISTER

XDEC

CONTROL

LOGIC

WORD

ADDRESS

COUNTER

SLAVE ADDRESS

COMPARATOR

START

STOP

LOGIC

WRITE

LOCKOUT

START CYCLE

DIN

R/W

LOAD

INC

SDA

SCL

VCC

DOUT

A2
A1
A0

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FM24C256 rev. B.3

FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

Ordering Information

Letter

Description

Blank

Tube

Tape and Reel

Package

8-pin DIP

8-pin SO8

Temp. Range

Blank

0 to 70

°C

-40 to +85

°C

Voltage Operating Range

Blank

4.5V to 5.5V

2.7V to 5.5V

2.7V to 5.5V and
<1

µA Standby Current

SCL Clock Frequency

Blank

100KHz

400KHz

Density

256

256K with write protect

CMOS

Interface

IIC - 2 Wire

Fairchild Non-Volatile
Memory

Part Number

Clock Frequency

Standby Current

FM24C256YYX

4.5V - 5.5V

µA typical

FM24C256LYYX

100KHz

2.7V - 5.5V

FM24C256LZYYX

µA max

FM24C256FYYX

4.5V - 5.5V

µA typical

FM24C256FLYYX

400KHz

2.7V - 5.5V

FM24C256FLZYYX

µA max

Part Number

Clock Frequency

Standby Current

FM24C256EYYX

4.5V - 5.5V

µA typical

FM24C256LEYYX

100KHz

2.7V - 5.5V

FM24C256LZEYYX

µA max

FM24C256FEYYX

4.5V - 5.5V

µA typical

FM24C256FLEYYX

400KHz

2.7V - 5.5V

FM24C256FLZEYYX

µA max

Commercial Temperature Range: 0

to +70

Industrial Temperature Range: -40

to +85

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FM24C256 rev. B.3

FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

Absolute Maximum Ratings

Ambient Storage Temperature

°C to +150°C

All Input or Output Voltages

with Respect to Ground

6.5V to 0.3V

Lead Temperature

(Soldering, 10 seconds)

+300

°C

ESD Rating

4000V min.

Operating Conditions

Ambient Operating Temperature

FM24C256/L/LZ

°C to +70°C

FM24C256F/FL/FLZ

°C to +70°C

FM24C256E/LE/LZE

-40

°C to +85°C

FM24C256FE/FLE/FLZE

-40

°C to +85°C

Positive Power Supply

FM24C256/E

4.5V to 5.5V

FM24C256F/FE

4.5V to 5.5V

FM24C256L/LZ

2.7V to 5.5V

FM24C256FL/FLZ

2.7V to 5.5V

FM24C256LE/LZE

2.7V to 5.5V

FM24C256FLE/FLZE

2.7V to 4.5V

Standard V

(4.5V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Units

Min

Typ

Max

CCA

Active Power Supply Current

SCL

= 100 kHz

0.5

1.0

SCL

= 400 kHz

Standby Current

= GND or V

µA

Input Leakage Current

= GND to V

0.1

µA

Output Leakage Current

OUT

= GND to V

0.1

µA

Input Low Voltage

0.3

x 0.3

Input High Voltage

x 0.7

+ 0.5

Output Low Voltage

= 2.1 mA

0.4

Low V

(2.7V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Units

Min

Typ

Max

CCA

Active Power Supply Current

SCL

= 100 kHz

0.5

1.0

SCL

= 400 kHz

Standby Current for L

= GND or V

= 4.5V - 5.5V

µA

(Note 1)

= GND or V

= 2.7V - 4.5V

Standby Current for LZ

= GND or V

= 4.5V - 5.5V

= GND or V

= 2.7V - 4.5V

0.1

Input Leakage Current

= GND to V

0.1

µA

Output Leakage Current

OUT

= GND to V

0.1

µA

Input Low Voltage

0.3

x 0.3

Input High Voltage

x 0.7

+ 0.5

Output Low Voltage

= 2.1 mA

0.4

Capacitance

= +25

°C, f = 100/400 KHz, V

= 5V

Symbol

Test

Conditions

Max

Units

I/O

Input/Output Capacitance (SDA)

I/O

= 0V

Input Capacitance (A0, A1, A2, SCL)

= 0V

Note 1: Typical values are for T

= 25

°C and nominal supply voltage (5V).

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FM24C256 rev. B.3

FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

AC Conditions of Test

Input Pulse Levels

x 0.1 to V

x 0.9

Input Rise and Fall Times

10 ns

Input & Output Timing Levels

x 0.5

Output Load

1 TTL Gate and C

= 100 pF

Read and Write Cycle Limits (Standard and Low V

Range - 2.7V-5.5V)

Symbol

Parameter

100 kHz

400 kHz

Units

Min

Max

Min

Max

SCL

SCL Clock Frequency

100

400

kHz

Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V

100

Pulse width)

SCL Low to SDA Data Out Valid

0.3

3.5

0.3

1.2

µs

BUF

Time the Bus Must Be Free before

4.7

1.3

µs

a New Transmission Can Start

HD:STA

Start Condition Hold Time

4.0

0.6

µs

LOW

Clock Low Period

4.7

1.5

µs

HIGH

Clock High Period

4.0

0.6

µs

SU:STA

Start Condition Setup Time

4.7

0.6

µs

(for a Repeated Start Condition)

HD:DAT

Data in Hold Time

µs

SU:DAT

Data in Setup Time

250

100

SDA and SCL Rise Time

0.3

µs

SDA and SCL Fall Time

300

SU:STO

Stop Condition Setup Time

4.7

0.6

µs

Data Out Hold Time

100

Write Cycle Time

(Note 2)

Note 2: The write cycle time (t

) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the

FM24C256 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address

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FM24C256 rev. B.3

FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

BACKGROUND INFORMATION (IIC Bus)

The IIC bus allows synchronous bidirectional communication be-
tween Transmitter/Receiver using the SCL (clock) and SDA (Data
I/O) lines. All communication must be started with a valid START
condition, concluded with a STOP condition and acknowledged by
the Receiver with an ACKNOWLEDGE condition.

In addition, since the IIC bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
control byte, must follow the START condition. For EEPROMs, the
first 4-bit of the control byte is 1010 binary for READ and WRITE
operations. This is then followed by the device selection bits A2, A1
and A0, and acts as the three most significant bits of the word
address.The final bit in the control byte determines the type of
operation performed (READ/WRITE). A "1" signifies a READ while
a "0" signifies a WRITE. The control byte is then followed by two bytes
that define the word address, which is then followed by the data byte.

The EEPROMs on the IIC bus may be configured in any manner
required, providing the total memory addressed does not exceed
512K bits (64K bytes). EEPROM memory addressing is controlled
by hardware configuring the A2, A1, and A0 pins (Device Address
pins) with pull-up or pull-down resistors. ALL UNUSED PINS
MUST BE GROUNDED (tied to V

Addressing an EEPROM memory location involves sending a
command string with the following information:

[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD-
DRESS]-[BYTE ADDRESS]

Pin Description

SERIAL CLOCK (SCL)

Definitions

Word

8 bits (byte) of data

Page

64 sequential addresses (one byte each) that
may be programmed during a "Page Write"
programming cycle.

Master

Any IIC device CONTROLLING the transfer of
data (such as a microcontroller).

Slave

Device being controlled (EEPROMS are
always considered Slaves).

Transmitter

Device currently SENDING data on the bus
(may be either a Master or Slave).

Receiver

Device currently receiving data on the bus
(Master or Slave).

The SCL input is used to clock all data into and out of the device.

SERIAL DATA (SDA)

SDA is a bidirectional pin used to transfer data to and from the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.

Device Address Inputs (A0, A1, A2)

Device address pins A0, A1, and A2 are connected to V

or V

to configure the EEPROM address for multiple device configura-
tion. A total of eight different devices can be attached to the same
SDA bus.

Write Protection (WP)

If WP is tied to V

, program WRITE operations onto the entire

array of the memory will not be executed. READ operations are
always available.

If WP is tied to V

or left floating (unconnected), normal memory

operation is enabled for READ/WRITE over the entire 256K bit
memory array.

This feature allows the user to assign the entire array of the memory
as ROM, which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.

Device Operation

The FM24C256xxx supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving devices as the receiver. The device
controlling the transfer is the master and the device that is con-
trolled is the slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations. There-
fore, the FM24C256xxx is considered a slave in all applications.

CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and are reserved for
indication of start and stop conditions.

Refer to Figures 1 and 2.

START CONDITION

All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
FM24C256xxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command until this
condition has been met.

STOP CONDITION

All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM24C256xxx to place the device in
the standby power mode.

;;

SCL

SDA

OUT

tLOW

tHIGH

tLOW

tAA

tDH

tBUF

tSU:STA

tHD:DAT

tHD:STA

tSU:DAT

tSU:STO

DS800023-3

Bus Timing

Note 3: SCL = Serial Clock Data

SDA = Serial Data I/O

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FM24C256 rev. B.3

FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

Write Cycle Timing

ACKNOWLEDGE

ACK (acknowledge) is a software convention used to indicate
successful data transfers. The transmitting device, either master or
slave, will release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to

Figure 3.

The FM24C256xxx device will always respond with an acknowl-
edge after recognition of a start condition and its slave address. If

Write Cycle Timing:

SDA

SCL

STOP

CONDITION

START

CONDITION

WORD n

8th BIT

ACK

tWR

SDA

SCL

DATA STABLE

DATA

CHANGE

SDA

SCL

START CONDITION

STOP CONDITION

DS800023-4

DS800023-5

Data Validity (Figure 1)

Definition of Start and Stop (Figure 2)

DS800023-6

both the device and a WRITE operation have been selected, the
FM24C256xxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.

In the READ mode the FM24C256xxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.

SCL FROM

MASTER

Data Output

from Transmitter

Data Output

from Receiver

START

ACKNOWLEDGE

Acknowledge Response from Receiver (Figure 3)

DS800023-7

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FM24C256 rev. B.3

FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

S
T

A
C
K

Bus Activity:

Master

SDA Line

1 0 1 0

Bus Activity

A
C
K

DATA

A
C
K

WORD

ADDRESS (1)

WORD

ADDRESS (0)

SLAVE

ADDRESS

S
T
A
R
T

DEVICE ADDRESSING

Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier. This is fixed as
1010 for all different FM24C256xxx devices.

The next three bits identify the device address. Address from 000
to 111 are acceptable thus allowing up to eight devices to be
connected to the IIC bus.

The last bit of the slave address defines whether a write or read
condition is requested by the master. A "1" indicates that a READ
operation is to be executed and a "0" initiates the WRITE mode.

A simple review: After the FM24C256xxx recognizes the start
condition, the device interfaced to the IIC bus waits for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the SDA line LOW with an acknowledge
signal and awaits further transmissions.

Write Operations

BYTE WRITE

For a WRITE operation, two additional address fields are required
after the control byte acknowledge. These are the word addresses
and comprise fifteen bits to provide access to any one of the 32K
words. The first byte indicates the high-order byte of the word
address. Only the seven least signicant bits can be changed, the
most significant bit is pre-assigned the value "0". Following the
acknowledgement from the first word address, the next byte
indicates the low-order byte of the word address. Upon receipt of
the word address, the FM24C256xxx responds with another
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time the
FM24C256xxx begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress, the device's
inputs are disabled and the device will not respond to any requests
from the master. Refer to

Figure 5 for the address, acknowledge

and data transfer sequence.

PAGE WRITE

The FM24C256xxx is capable of 64 byte page write operation. It
is initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data word is
transferred, the master can transmit up to 63 more words. After
the receipt of each word, the device responds with an acknowl-
edge.

After the receipt of each word, the internal address counter
increments to the next address and the next SDA data is ac-
cepted. If the master should transmit more than 64 words prior to
generating the stop condition, the address counter will "roll over"
and the previous written data will be overwritten. As with the byte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to

Figure 6 for the address, acknowl-

edge and data transfer sequence.

Acknowledge Polling

Once the stop condition is isssued to indicate the end of the host's
write operation, the FM24C256xxx initiates the internal write
cycle. ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address for a write
operation. If the FM24C256xxx is still busy with the write opera-
tion, no ACK will be returned. If the device has completed the write
operation, an ACK will be returned and the host can then proceed
with the next read or write operation.

DS800023-8

Byte Write (Figure 5)

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FM24C256 rev. B.3

FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

Write Protection

Programming of the memory array will not take place if the WP pin
is connected to V

. The device will accept control and word

addresses; but if the memory accessed is write protected by the
WP pin, the FM24C256xxx will not generate an acknowledge after
the first byte of data has been received, and thus the program
cycle will not be started when the stop condition is asserted.

Read Operation

Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to "1". There are three basic read operations: current
address read, random read and sequential read.

CURRENT ADDRESS READ

Internally the FM24C256xxx contains an address counter that
maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n+1. Upon receipt of the slave address with R/W set to
"1," the FM24C256xxx issues an acknowledge and transmits the
eight bit word. The master will not acknowledge the transfer but
does generate a stop condition, and therefore discontinues trans-
mission. Refer to

Figure 7 for the sequence of address, acknowl-

edge and data transfer.

RANDOM READ

Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address

with the R/W bit set to "1", the master must first perform a "dummy"
write operation. The master issues a start condition, a slave
address, and then the word address to be read. After the word
address acknowledge, the master immediately reissues the start
condition and the slave address with the R/W bit set to "1". This will
be followed by an acknowledge from the FM24C256xxx and then
by the eight bit word. The master will not acknowledge the transfer
but does generate the stop condition, and therefore the
FM24C256xxx discontinues transmission. Refer to

Figure 8 for

the address, acknowledge, and data transfer sequence.

SEQUENTIAL READ

Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The FM24C256xxx continues to output data for each ac-
knowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.

The data output is sequential, with the data from address n,
followed by the data n+1. The address counter for read operations
increments all word address bits, allowing the entire memory
contents to be serially read during one operation. After the entire
memory has been read, the counter "rolls over" and the
FM24C256xxx continues to output data for each acknowledge
received. Refer to

Figure 9 for the address, acknowledge, and

data transfer sequence.

S
T

A
C
K

Bus Activity:

Master

SDA Line

1 0 1 0

Bus Activity

A
C
K

DATA n

DATA n+63

A
C
K

WORD

ADDRESS (1)

WORD

ADDRESS (0)

SLAVE

ADDRESS

S
T
A
R
T

DS800023-9

Page Write (Figure 6)

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FM24C256 rev. B.3

FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

Physical Dimensions

inches (millimeters) unless otherwise noted

Molded Dual-In-Line Package (N)

Order Number FM24C256xxxN or FM24C256xxxEN

Package Number N08E

0.373 - 0.400

(9.474 - 10.16)

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 ± 0.127)

0.032 ± 0.005

(0.813 ± 0.127)

Pin #1

Option 2

RAD

0.145 - 0.200

(3.683 - 5.080)

0.130 ± 0.005

(3.302 ± 0.127)

0.125 - 0.140

(3.175 - 3.556)

0.020

(0.508)

Min

0.018 ± 0.003

(0.457 ± 0.076)

90° ± 4°

Typ

0.100 ± 0.010

(2.540 ± 0.254)

0.040

(1.016)

0.039

(0.991)

Typ.

20° ± 1°

0.065

(1.651)

0.050

(1.270)

0.060

(1.524)

Pin #1 IDENT

Option 1

0.280 MIN

0.300 - 0.320

(7.62 - 8.128)

0.030

(0.762)

MAX

0.125

(3.175)

DIA

NOM

0.009 - 0.015

(0.229 - 0.381)

0.045 ± 0.015

(1.143 ± 0.381)

0.325

+0.040

-0.015

8.255

+1.016

-0.381

95° ± 5°

0.090

(2.286)

(7.112)

IDENT

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Europe

Hong Kong

Japan Ltd.

Customer Response Center

Fax:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

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Tel. 1-888-522-5372

Deutsch

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Tel:

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