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FM27C040 Rev. A
FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
FM27C040
4,194,304-Bit (512K x 8) High Performance
CMOS EPROM
General Description
The FM27C040 is a high performance, 4,194,304-bit Electrically
Programmable UV Erasable Read Only Memory. It is organized
as 512K words of 8 bits each. Its pin-compatibility with byte-wide
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.
The "Don't Care" feature on V
PP
during read operations allows
memory expansions from 1M to 8 Mbits with no printed circuit
board changes.
The FM27C040 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 120ns access time provides high speed
operation with high-performance CPUs. The FM27C040 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The FM27C040 is manufactured using Fairchild's advanced CMOS
AMGTM EPROM technology.
Block Diagram
January 2000
Features
I High performance CMOS
-- 120, 150ns access time*
I Simplified upgrade path
--V
PP
is a "Don't Care" during normal read operation
I Manufacturer's identification code
I JEDEC standard pin configuration
-- 32-pin PDIP
-- 32-pin PLCC
-- 32-pin CERDIP
DS800033-1
AMGTM is a trademark of WSI, Inc.
1999 Fairchild Semiconductor Corporation
Output Enable,
Chip Enable, and
Program Logic
Y Decoder
X Decoder
. .
. . . . . . .
Output
Buffers
Y Gating
4,194,304-Bit
Cell Matrix
Data Outputs O0 - O7
VCC
GND
VPP
OE
CE/PGM
A0 - A18
Address
Inputs
*Note: New revision meets 70ns. Please check with factory for availability.
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FM27C040 Rev. A
FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Connection Diagrams
Note:
Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C040 pin.
Commercial Temperature Range
(0
C to +70
C) V
CC
= 5V
10%
Parameter/Order Number
Access Time (ns)
FM27C040 Q, N, V 90
90
FM27C040 Q, N, V 120
120
FM27C040 Q, N, V 150
150
Extended Temperature Range
(-40
C to +85
C) V
CC
= 5V
10%
Parameter/Order Number
Access Time (ns)
FM27C040 QE, NE, VE 90
90
FM27C040 QE, NE, VE 120
120
FM27C040 QE, NE, VE 150
150
Package Types: FM27C040 Q, N,V XXX
Q = Quartz-Windowed Ceramic DIP
N = Plastic DIP
V = PLCC
All packages conform to the JEDEC standard.
All versions are guaranteed to function for slower speeds.
Pin Names
A0A18
Addresses
CE/PGM
Chip Enable/Program
OE
Output Enable
O0O7
Outputs
XX
Don't Care (During Read)
DS800033-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
XX/V
PP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
27C010
XX/V
PP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
27C010
FM27C040
V
CC
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE/PGM
O7
O6
O5
O4
O3
V
CC
XX/PGM
NC
A14
A13
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
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FM27C040 Rev. A
FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings
(Note 1)
Storage Temperature
-65
C to +150C
All Input Voltages except A9 with
Respect to Ground
-0.6V to +7V
V
PP
and A9 with Respect to Ground
-0.6V to +14V
V
CC
Supply Voltage with
Respect to Ground
-0.6V to +7V
ESD Protection
>2000V
All Output Voltages with
Respect to Ground
V
CC
+1.0V to GND - 0.6V
Operating Range
Range
Temperature
V
CC
Tolerance
Commercial
0
C to +70C
+5V
10%
Industrial
-40
C to +85C
+5V
10%
Read Operation
DC Electrical Characteristics
Over operating range with V
PP
= V
CC
Symbol
Parameter
Test Conditions
Min
Max
Units
V
IL
Input Low Level
-0.5
0.8
V
V
IH
Input High Level
2.0
V
CC
+1
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
0.4
V
V
OH
Output High Voltage
I
OH
= -2.5 mA
3.5
V
I
SB1
V
CC
Standby Current (CMOS)
CE = V
CC
0.3V
100
A
I
SB2
V
CC
Standby Current
CE = V
IH
1
mA
I
CC
V
CC
Active Current
CE = OE = V
IL
,
f=5 MHz
30
mA
I/O = 0 mA
I
PP
V
PP
Supply Current
V
PP
= V
CC
10
A
V
PP
V
PP
Read Voltage
V
CC
- 0.4
V
CC
V
I
LI
Input Load Current
V
IN
= 5.5V or GND
-1
1
A
I
LO
Output Leakage Current
V
OUT
= 5.5V or GND
-10
10
A
AC Electrical Characteristics
Over operating range with V
PP
= V
CC
Symbol
Parameter
120
150
Units
Min
Max
Min
Max
t
ACC
Address to Output Delay
120
150
t
CE
CE to Output Delay
120
150
t
OE
OE to Output Delay
50
50
t
DF
Output Disable to
45
55
ns
(Note 2)
Output Float
t
OH
Output Hold from Addresses CE or OE ,
0
0
(Note 2)
Whichever Occurred First
Capacitance
T
A
= +25
C, f = 1 MHz (Note 2)
Symbol
Parameter
Conditions
Typ
Max
Units
C
IN
Input Capacitance
V
IN
= 0V
9
15
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
15
pF
4
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FM27C040 Rev. A
FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
Input Rise and Fall Times
5 ns
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs
0.8V and 2V
Outputs`
0.8V and 2V
AC Waveforms
(Notes 6, 7, 9)
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4: The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE .
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
F ceramic capacitor be used on every device
between V
CC
and GND.
Note 7: The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
A.
C
L
: 100 pF includes fixture capacitance.
Note 9: V
PP
may be connected to V
CC
except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Addresses Valid
Valid Output
Hi-Z
2V
0.8V
2V
0.8V
2V
0.8V
ADDRESSES
OUTPUT
CE
OE
tCE
2V
0.8V
(Note 3)
(Note 3)
tDF
(Note 4, 5)
(Note 4, 5)
tOH
Hi-Z
tOE
ACC
t
CF
t
DS800033-4
5
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FM27C040 Rev. A
FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
Programming Waveform
(Note 13)
Programming Characteristics
(Notes 11, 12, 13, 14)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
AS
Address Setup Time
1
s
t
OES
OE Setup Time
1
s
t
DS
Data Setup Time
1
s
t
VPS
V
PP
Setup Time
1
s
t
VCS
V
CC
Setup Time
1
s
t
AH
Address Hold Time
0
s
t
DH
Data Hold Time
1
s
t
DF
Output Enable to Output Float Delay
CE/PGM = X
0
60
ns
t
PW
Program Pulse Width
45
50
105
s
t
OE
Data Valid from OE
CE/PGM = X
100
ns
I
PP
V
PP
Supply Current during
CE/PGM = V
IL
30
mA
Programming Pulse
I
CC
V
CC
Supply Current
30
mA
T
A
Temperature Ambient
20
25
30
C
V
CC
Power Supply Voltage
6.25
6.5
6.75
V
V
PP
Programming Supply Voltage
12.5
12.75
13.0
V
t
FR
Input Rise, Fall Time
5
ns
V
IL
Input Low Voltage
-0.1
0.0
0.45
V
V
IH
Input High Voltage
2.4
4.0
V
t
IN
Input Timing Reference Voltage
0.8
2.0
V
t
OUT
Output Timing Reference Voltage
0.8
2.0
V
Note 11: Fairchild's standard product warranty applies only to devices programmed to specifications described herein.
Note 12: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removed from a board with
voltage applied to V
PP
or V
CC
.
Note 13: The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1
F capacitor is required across V
PP
, V
CC
to GND to suppress spurious voltage transients
which may damage the device.
Note 14: During power up the CE/PGM pin must be brought high (
V
IH
) either coincident with or before power is applied to V
PP
.
t
AS
t
AH
Program
Program
Verify
Address N
t
DF
Data Out Valid
ADD N
Data In Stable
ADD N
Hi-Z
t
DS
t
DH
t
VCS
t
VPS
t
PW
t
OES
t
OE
2V
0.8V
2V
0.8V
6.25V
12.75V
2V
0.8V
2V
0.8V
ADDRESSES
DATA
V
PP
CE/PGM
OE
V
CC
DS800033-5
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