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REV. 1.5 11/10/00
Features
3-channels
108 Ms/s conversion rate
Programmable Clamps
500ps PLL clock jitter
Adjustable Gain and offset
Internal Reference Voltage
I
2
C/SMBus compatible Serial Port
100-pin package
Applications
Flat panel displays and projectors
RGB Graphics Processing
Description
As a fully integrated analog interface, the FMS9874 can directly
digitize RGB graphics with resolutions up to 1024 x 768/85Hz
and 1280 x 1024/60Hz; or using alternate pixel sampling,
1600 x 1200/75Hz. ADC sampling clock can be derived from
either an external source or incoming horizontal sync signal
using the internal PLL. Output data is 24-bit RGB. Setup and
control is via registers, accessible through an SMBus/I
2
C com-
patible serial port.
Input amplitude range is 5001000mV with either DC or AC
coupling. Lower reference of AC coupled inputs is estab-
lished with input clamps that are either internally generated
or externally provided.
Common to the three channels are clamp pulses, a bandgap
reference voltage and clocks derived from a PLL or an external
source. Digital data levels are 2.53.3 volt CMOS compliant.
Power can be derived from a single +3.3 Volt power supply.
Package is a 100-lead MQFP. Performance specifications are
guaranteed over 0C to 70C range.
Block Diagram
Clamp
A/D
Converter
A/D
Converter
A/D
Converter
Gain &
Offset
Clamp
Gain &
Offset
Clamp
Gain &
Offset
DR
7-0
DG
7-0
DB
7-0
R
IN
G
IN
B
IN
A
0
A
1
Control
SDA
SCL
PWRDN
PLL
SYNC
STRIPPER
Timing
Generator
HSIN
ACS
IN
COAST
XCK
LPF
PXCK
HS
DCS
OUT
DCK
DCK
HSOUT
INVSCK
VREFIN
VREFOUT
Reference
CLAMP
ICLAMP
SCK
FMS9874
Graphics Digitizer
3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps
PRODUCT SPECIFICATION
FMS9874
2
REV. 1.5 11/10/00
Architectural Overview
Three separate digitizer channels are controlled by common
timing signals derived from the Timing Generator. A/D clock
signals can be derived from either a PLL or an external clock
XCK. With the PLL selected, A/D clocks track the incoming
horizontal sync signal connected to the HSIN input. Setup is
controlled by registers that are accessible through the serial
interface.
Conversion Channels
Typical RGB graphics signals, R
IN
, G
IN
, B
IN
are ground ref-
erenced with 700mV amplitude. If a sync signal is embedded
then the usual format is sync on green with the sync tip at
ground, the black level elevated to 300mV and peak green at
1000mV.
AC coupled video signals must be level shifted to establish
the lower level of the conversion range by clamping to the
black level of the back porch (see Figure 1). Clamp pulses
are derived from internal Timing and Control logic or from
the external CLAMP input.
Figure 1. Clamping to the back-porch
Gain and Offset
Gain and Offset registers serve two functions: adjustment of
contrast and brightness by setting RGB values in tandem;
matching the gain and offsets between channels, by setting
RGB values individually to obtain the same output levels.
A/D conversion range can be matched to the amplitude of the
incoming video signal by programming Gain Registers GR,
GG and GB, which vary sensitivity (LSB/volt) over a 2:1
range. Incoming video signal amplitudes varying from 0.5 to
1.0 volt can be accommodated.
Input offset voltage of each converter is programmable in 1
LSB steps through the 6-bit OSR, OSG and OSB registers.
Range of adjustment is equivalent to 31 to +32 LSB.
A/D Converter
Each A/D converter digitizes the analog input into 8-bit data
words. Latency is 55
1
/
2
clock cycles, depending upon the
state of CHINV.
V
REFIN
is the source of reference voltage for the three A/D
converters. V
REFIN
can be connected to either the internal
bandgap voltage, V
REFOUT
or an external voltage.
Output Data Configuration
Output data number format for each channel is binary:
00 corresponds to the lowest input; FF corresponds to the
highest input.
Timing and Control
Timing and Control logic encompasses the Timing Generator,
PLL and Serial Interface.
Timing Generator
All internal clock and synchronization signals are generated
by the Timing Generator. Master Clock source is either the
PLL or the external clock input, XCK. Bit XCKSEL selects
the Master Clock source. Two clocks are generated.
Sampling clock, SCK is supplied to all three A/D converters.
Phase of SCK can be adjusted in 32 11.25 degree phase
increments using the 5-bit PHASE register.
DCK is the output data clock. DCK and DCK are supplied as
outputs for synchronizing data transfer from the digitizer
outputs.
Horizontal sync applied to the input, HS
IN
is propagated by
the Timing and Control to the HS
OUT
output with a delay
that aligns leading and trailing edges with the output data.
Phase Locked Loop
With a horizontal sync signal connected to the HSIN input
pin, the PLL generates a high frequency internal clock signal,
PXCK that is fed to the Timing and Control logic. Frequency
of PXCK is set by the register programmable PLL divide ratio,
PLLN.
COAST is an input that disables the PLL lock to the horizontal
sync input, HSIN. If HSIN is to be disregarded for a period
such as the vertical sync interval, COAST allows the VCO
frequency to be maintained. Missing horizontal sync pulses
during the vertical interval can cause tearing at the top of a
picture, if COAST is not used.
Two pixels per clock mode is set by programming the PLL
to half the pixel rate. By toggling the INVCK pin between
frames, even and odd pixels can be read on alternate frames.
Serial Interface
Registers are accessed through an I
2
C/SMBus compatible
serial port. Four serial addresses are pin selectable.
R
IN
, G
IN
, B
IN
ICLAMP
FMS9874
PRODUCT SPECIFICATION
REV. 1.5 11/10/00
3
Pin Assignments
100-Lead MQFP (KG)
No.
Name
No.
Name
No.
Name
No.
Name
1
GND
26
GND
51
DB
7
76
DR
7
2
R
IN
27
GND
52
DB
6
77
DR
6
3
V
DDA
28
HSIN
53
DB
5
78
DR
5
4
GND
29
COAST
54
DB
4
79
DR
4
5
V
DDA
30
GND
55
DB
3
80
DR
3
6
GND
31
V
DDP
56
DB
2
81
DR
2
7
ACS
IN
32
XCK
57
DB
1
82
DR
1
8
G
IN
33
LPF
58
DB
0
83
DR
0
9
V
DDA
34
NC
59
GND
84
GND
10
GND
35
GND
60
V
DDO
85
V
DDO
11
V
DDA
36
V
DDP
61
GND
86
DCK
12
GND
37
GND
62
V
DDO
87
DCK
13
B
IN
38
V
DDP
63
DG
7
88
HS
OUT
14
V
DDA
39
GND
64
DG
6
89
DCS
OUT
15
GND
40
GND
65
DG
5
90
GND
16
V
DDA
41
GND
66
DG
4
91
V
DDO
17
GND
42
NC
67
DG
3
92
GND
18
INVSCK
43
NC
68
DG
2
93
GND
19
CLAMP
44
NC
69
DG
1
94
GND
20
SDA
45
NC
70
DG
0
95
V
DDA
21
SCL
46
NC
71
GND
96
PWRDN
22
A
0
47
NC
72
V
DDO
97
V
REFOUT
23
A
1
48
NC
73
NC
98
V
REFIN
24
V
DDP
49
GND
74
NC
99
V
DDA
25
V
DDP
50
V
DDO
75
NC
100
V
DDA
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PRODUCT SPECIFICATION
FMS9874
4
REV. 1.5 11/10/00
Pin Descriptions
Pin Name
Pin No.
Type/Value
Pin Function Description
Converter Channels
R
IN
, G
IN
, B
IN
2, 8, 13
Input
Analog Inputs.
DR
7-0
7683
Output
Red Channel A Data Output.
DG
7-0
6370
Output
Green Channel A Data Output.
DB
7-0
5158
Output
Blue Channel A Data Output.
Timing Generator
CLAMP
19
Input
External Clamp Input.
INVSCK
18
Input
Invert Sampling Clock.
Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 216Ms/s.
XCK
32
Input
External Clock input.
Enabled if register bit, XCKSEL = H. Replaces
PXCK clock generated by PLL. If unused, connect to ground through a
10k
resistor.
DCK
86
Output
Output Data Clock.
Clock for strobing output data to external logic.
DCK
87
Output
Output Data Clock Inverted.
Inverted clock for strobing output data to
external logic.
HSOUT
88
Output
Horizontal Sync Output.
Reconstructed HSYNC delayed by
FMS9874 latency and synchronized with DCK. Leading edge is
synchronized to start of data output. Polarity is always active HIGH.
Phase Locked Loop
HSIN
28
Schmitt
Horizontal Sync input.
Schmitt trigger threshold is 1.5V. A 5V source
should be clamped at 3.3V or current limited to prevent overdriving
ESD protection diodes.
COAST
29
Input
PLL Coast.
Maintain frequency of PLL output clock PXCK,
disregarding HSIN. If horizontal sync is missing during the vertical sync
interval, PXCK clock frequency can be maintained by asserting
COAST.
LPF
33
Passive
PLL Low Pass Filter.
Connect recommended PLL filter to LPF pin.
(see Figure 13.)
Sync Stripper
ACS
IN
7
Analog Composite Sync Input.
Input to sync stripper with 150mV
threshold.
DCS
OUT
89
Digital Composite Sync Output. Output from sync stripper.
Control
SDA
20
Bi-directional Serial Port Data. Bi-directional data.
SCL
21
Input
Serial Port Clock. Clock input.
A
0
22
Input
Address bit 0. Lower bit of serial port address.
A
1
23
Input
Address bit 1. Upper bit of serial port address.
PWRDN
96
Input
Power Down/Output Control. Powers down the FMS9874 and
tri-states the outputs.
PRODUCT SPECIFICATION
FMS9874
5
REV. 1.5 11/10/00
Pin Descriptions
Addressable Memory
Register Map
Pin
Name
Pin No.
Pin Function Description
Power and Ground
V
DDA
3, 5, 9, 11, 14, 16, 95, 99, 100 ADC Supply Voltages. Provide a quiet noise free voltage.
V
DDP
24, 25, 31, 36, 38
PLL Supply Voltage. Most sensitive supply voltage. Provide a very
quiet noise free voltage.
V
DDO
50, 60, 62, 72, 85, 91
Digital Output Supply Voltage. Decouple judiciously to avoid
propagation of switching noise.
GND
1, 4, 6, 10, 12, 15, 17, 26, 27,
30, 35, 37, 39, 40, 41, 49, 59,
61, 71, 84, 90, 92, 93, 94
Ground. Returns for all power supplies. Connect ground pins to a
solid ground plane.
V
REFIN
98
Voltage Reference Input. Common reference input to RGB
converters. Connect to VREFOUT, if internal reference is used.
V
REFOUT
97
Voltage Reference Output. Internal band-gap reference output. Tie to
ground through a 0.1F capacitor.
Name
Address
Function
Default (hex)
PLLN
11-4
00
PLL divide ratio, MSBs. PLLN + 1 = total number of
pixels per horizontal line.
69 (1693)
PLLN
3-0
01
PLL divide ratio, LSBs. PLLN + 1 = total number of pixels
per horizontal line. PLLN
3-0
stored in the four upper
register bits 7-4.
D0 (1693)
GR
7-0
02
Gain, red channel. Adjustable from 70 to 140%.
80
GG
7-0
03
Gain, green channel. Adjustable from 70 to 140%.
80
GB
7-0
04
Gain, blue channel. Adjustable from 70 to 140%.
80
OSR
5-0
05
Offset, red channel. OSR
5-0
stored in the six upper
register bits 7-2.Default value is decimal 32.
80
OSG
5-0
06
Offset, green channel. OSR
5-0
stored in the six upper
register bits 7-2. Default value is decimal 32.
80
OSB
5-0
07
Offset, blue channel. OSR
5-0
stored in the six upper
register bits 7-2. Default value is decimal 32.
80
CD
7-0
08
Clamp delay. Delay in pixels from trailing edge of
horizontal sync.
80
CW
7-0
09
Clamp width. Width of clamp pulse in pixels.
80
CONFIG 1
0A
Configuration Register No. 1
F4
PHASE
7-0
0B
Sampling clock phase. PHASE
4-0
stored in upper
register bits 7-3. PHASE sets the sampling clock phase in
11.25 increments. Default value is decimal 16.
10
PLLN
30
X X X X
X
OSR
50
X X
OSG
50
X X
OSB
50
X X
PHASE
40
X X X
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