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REV. 1.2.2 12/7/01
Features
3-channels
100/140/175 Ms/s conversion rate
Programmable Clamps
Adjustable Gain and offset
Internal Reference Voltage
I
2
C/SMBus compatible Serial Port
Pin Compatible with AD9884A
Applications
Flat panel displays and projectors
RGB Graphics Processing
Description
As a fully integrated analog interface, the FMS9884A can digi-
tize RGB graphics with resolutions up to 1600 x 1200/65Hz
refresh or 1600 x 1200/85Hz using alternate pixel sampling.
ADC sampling clock can be derived from either an external
source or incoming horizontal sync signal using the internal
PLL. Output data is released through either one port at full
rate or both ports, each running at half-rate. Setup and control
is via registers, accessible through an SMBus/I
2
C compatible
serial port.
Input amplitude range is 5001000mV with either DC or AC
coupling. Lower reference of AC coupled inputs is estab-
lished with input clamps that are either internally generated
or externally provided.
Common to the three channels are clamp pulses, a bandgap
reference voltage and clocks derived from a PLL or an external
source. Digital data levels are 2.53.3 volt CMOS compliant.
Power can be derived from a single +3.3 Volt power supply. For
175 MHz applications see special V
PLL
requirements. Package
is a 128-lead MQFP. Performance specifications are guaran-
teed over 0C to 70C range.
Product Number
Speed
FMS9884AKAC100
108 Ms/s
FMS9884AKAC140
140 Ms/s
FMS9884AKAC175
175 Ms/s
Block Diagram
Clamp
A/D
Converter
A/D
Converter
A/D
Converter
Gain &
Offset
Switch
Clamp
Gain &
Offset
Switch
Clamp
Gain &
Offset
Switch
DRA
7-0
DGA
7-0
DBA
7-0
RPD
7-0
GPD
7-0
BPD
7-0
R
IN
G
IN
B
IN
A
0
A
1
DRB
7-0
DGB
7-0
DBB
7-0
Control
SDA
SCL
PWRDN
PLL
SYNC
STRIPPER
Timing
Generator
HSIN
ACS
IN
COAST
XCK
LPF
PXCK
HS
DCS
OUT
DCK
DCK
HSOUT
INVSCK
VREFIN
VREFOUT
Reference
CLAMP
ICLAMP
SCK
FMS9884A
Graphics Digitizer
3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps
PRODUCT SPECIFICATION
FMS9884A
2
REV. 1.2.2 12/7/01
Architectural Overview
Three separate digitizer channels are controlled by common
timing signals derived from the Timing Generator. A/D clock
signals can be derived from either a PLL or an external clock
XCK. With the PLL selected, A/D clocks track the incoming
horizontal sync signal connected to the HSIN input. Setup is
controlled by registers that are accessible through the serial
interface.
Conversion Channels
Typical RGB graphics signals, R
IN
, G
IN
, B
IN
are ground ref-
erenced with 700mV amplitude. If a sync signal is embedded
then the usual format is sync on green with the sync tip at
ground, the black level elevated to 300mV and peak green at
1000mV.
AC coupled video signals must be level shifted to establish
the lower level of the conversion range by clamping to the
black level of the back porch (see Figure 1). Clamp pulses
are derived from internal Timing and Control logic or from
the external CLAMP input.
Figure 1. Clamping to the back-porch
Gain and Offset
Gain and Offset registers serve two functions: adjustment of
contrast and brightness by setting RGB values in tandem;
matching the gain and offsets between channels, by setting
RGB values individually to obtain the same output levels.
A/D conversion range can be matched to the amplitude of the
incoming video signal by programming Gain Registers GR,
GG and GB, which vary sensitivity (LSB/volt) over a 2:1
range. Incoming video signal amplitudes varying from 0.5 to
1.0 volt can be accommodated.
Input offset voltage of each converter is programmable in 1
LSB steps through the 6-bit OSR, OSG and OSB registers.
Range of adjustment is equivalent to 31 to +32 LSB.
A/D Converter
Each A/D converter digitizes the analog input into 8-bit data
words. Latency is 56
1
/
2
clock cycles, depending upon the
data out format.
V
REFIN
is the source of reference voltage for the three A/D
converters. V
REFIN
can be connected to either the internal
bandgap voltage, V
REFOUT
or an external voltage.
Output Data Configuration
Output data number format for each channel is binary: 00 cor-
responds to the lowest input; FF corresponds to the highest
input. Data can be released in either of two timing formats:
1.
Single 8-bit port at pixel rates up to 175Ms/s.
2.
Dual 8-bit ports, each running at half the conversion
rate. Maximum rate is 88Ms/s per port. Data streams
may be parallel or interleaved.
Timing and Control
Timing and Control logic encompasses the Timing Generator,
PLL and Serial Interface.
Timing Generator
All internal clock and synchronization signals are generated
by the Timing Generator. Master Clock source is either the
PLL or the external clock input, XCK. Bit XCKSEL selects
the Master Clock source. Two clocks are generated.
Sampling clock, SCK is supplied to all three A/D converters.
Phase of SCK can be adjusted in 32 11.25 degree phase
increments using the 5-bit PHASE register.
DCK is the output data clock. DCK and DCK are supplied as
outputs for synchronizing data transfer from the digitizer
outputs.
Horizontal sync applied to the input, HS
IN
is propagated by
the Timing and Control to the HS
OUT
output with a delay
that aligns leading and trailing edges with the output data.
Phase Locked Loop
With a horizontal sync signal connected to the HSIN input
pin, the PLL generates a high frequency internal clock signal,
PXCK that is fed to the Timing and Control logic. Frequency
of PXCK is set by the register programmable PLL divide
ratio, PLLN.
COAST is an input that disables the PLL lock to the horizontal
sync input, HSIN. If HSIN is to be disregarded for a period
such as the vertical sync interval, COAST allows the VCO
frequency to be maintained. Omission of horizontal sync
pulses during the vertical interval can cause tearing at the top
of a picture, if COAST is not used.
Two pixels per clock mode is set by programming the PLL
to half the pixel rate. By toggling the INVCK pin between
frames, even and odd pixels can be read on alternate frames.
Serial Interface
Registers are accessed through an I
2
C/SMBus compatible
serial port. Four serial addresses are pin selectable.
R
IN
, G
IN
, B
IN
ICLAMP
FMS9884A
PRODUCT SPECIFICATION
REV. 1.2.2 12/7/01
3
Pin Assignments
(128-Lead MQFP (KA) Package)
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
GND
VDDO
DCK
DCK
HSOUT
DCSOUT
GND
VDDO
GND
GND
GND
VDDA
PWRDN
VREFOUT
VREFIN
VDDA
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
VDDO
GND
GND
GND
VDDP
GND
VDDP
GND
NC
LPF
XCK
VDDP
GND
COAST
HSIN
GND
95
94
93
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
DRB0
DRB1
DRB2
DRB3
DRB4
DRB5
DRB6
DRB7
VDDO
GND
DGA0
DGA1
DGA2
DGA3
DGA4
DGA5
DGA6
DGA7
VDDO
GND
DGB0
DGB1
DGB2
DGB3
DGB4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
NC
VDDA
GND
GND
RIN
VDDA
GND
VDDA
VDDA
GND
GND
ACSIN
GIN
VDDA
GND
VDDA
VDDA
GND
GND
BIN
VDDA
GND
VDDA
74
73
72
71
70
69
68
67
66
65
102
101
100
DGB5
DGB6
DGB7
VDDO
GND
DBA0
DBA1
DBA2
DBA3
DBA4
DBA5
DBA6
DBA7
26
27
28
29
30
31
32
33
34
35
36
37
38
GND
INVSCK
CLAMP
SDA
SCL
A0
A1
VDDP
VDDP
GND
NC
NC
NC
103
104
105
106
107
108
109
110
111
112
GND
VDDO
DRA7
DRA6
DRA5
DRA4
DRA3
DRA2
DRA1
DRA0
64
63
62
61
60
59
58
57
56
55
VDDO
GND
DBB0
DBB1
DBB2
DBB3
DBB4
DBB5
DBB6
DBB7
PRODUCT SPECIFICATION
FMS9884A
4
REV. 1.2.2 12/7/01
Pin Assignments
No.
Name
No.
Name
No.
Name
No.
Name
1
NC
33
V
DDP
65
DBA
7
97
DRB
5
2
NC
34
V
DDP
66
DBA
6
98
DRB
4
3
NC
35
GND
67
DBA
5
99
DRB
3
4
V
DDA
36
NC
68
DBA
4
100
DRB
2
5
GND
37
NC
69
DBA
3
101
DRB
1
6
GND
38
NC
70
DBA
2
102
DRB
0
7
R
IN
39
GND
71
DBA
1
103
GND
8
V
DDA
40
HSIN
72
DBA
0
104
V
DDO
9
GND
41
COAST
73
GND
105
DRA
7
10
V
DDA
42
GND
74
V
DDO
106
DRA
6
11
V
DDA
43
V
DDP
75
DGB
7
107
DRA
5
12
GND
44
XCK
76
DGB
6
108
DRA
4
13
GND
45
LPF
77
DGB
5
109
DRA
3
14
ACS
IN
46
NC
78
DGB
4
110
DRA
2
15
G
IN
47
GND
79
DGB
3
111
DRA
1
16
V
DDA
48
V
DDP
80
DGB
2
112
DRA
0
17
GND
49
GND
81
DGB
1
113
GND
18
V
DDA
50
V
DDP
82
DGB
0
114
V
DDO
19
V
DDA
51
GND
83
GND
115
DCK
20
GND
52
GND
84
V
DDO
116
DCK
21
GND
53
GND
85
DGA
7
117
HS
OUT
22
B
IN
54
V
DDO
86
DGA
6
118
DCS
OUT
23
V
DDA
55
DBB
7
87
DGA
5
119
GND
24
GND
56
DBB
6
88
DGA
4
120
V
DDO
25
V
DDA
57
DBB
5
89
DGA
3
121
GND
26
GND
58
DBB
4
90
DGA
2
122
GND
27
INVSCK
59
DBB
3
91
DGA
1
123
GND
28
CLAMP
60
DBB
2
92
DGA
0
124
V
DDA
29
SDA
61
DBB
1
93
GND
125
PWRDN
30
SCL
62
DBB
0
94
V
DDO
126
V
REFOUT
31
A
0
63
GND
95
DRB
7
127
V
REFIN
32
A
1
64
V
DDO
96
DRB
6
128
V
DDA
FMS9884A
PRODUCT SPECIFICATION
REV. 1.2.2 12/7/01
5
Pin Descriptions
Pin Name
Pin No.
Type/Value
Pin Function Description
Converter Channels
R
IN
, G
IN
, B
IN
7, 15, 22
Input
Analog Inputs.
DRA
7-0
105112
Output
Red Channel Port A Data Output. Full rate/half rate, interleaved/
parallel data depending upon selected mode.
DRB
7-0
95102
Output
Red Channel Port B Data Output. Active for dual port mode only with
interleaved/parallel outputs. High impedance when inactive.
DGA
7-0
8592
Output
Green Channel Port A Data Output. See red channel port A.
DGB
7-0
7582
Output
Green Channel Port B Data Output. See red channel port B.
DBA
7-0
6572
Output
Blue Channel Port A Data Output. See red channel port A.
DBB
7-0
5562
Output
Blue Channel Port B Data Output. See red channel port B.
Timing Generator
CLAMP
28
Input
External Clamp Input.
INVSCK
27
Input
Invert Sampling Clock. Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 350Ms/s.
XCK
44
Input
External Clock input. Enabled if register bit, XCKSEL = H. Replaces
PXCK clock generated by PLL. If unused, connect to ground through a
10k
resistor.
DCK
115
Output
Output Data Clock. Clock for strobing output data to external logic.
DCK
116
Output
Output Data Clock Inverted. Inverted clock for strobing output data to
external logic.
HSOUT
117
Output
Horizontal Sync Output. Reconstructed HSYNC delayed by
FMS9884A latency and synchronized with DCK. Leading edge is
synchronized to start of data output. Polarity is always active HIGH.
Phase Locked Loop
HSIN
40
Schmitt
Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source
should be clamped at 3.3V or current limited to prevent overdriving
ESD protection diodes.
COAST
41
Input
PLL Coast. Maintain frequency of PLL output clock PXCK,
disregarding HSIN. If horizontal sync is missing during the vertical sync
interval, PXCK clock frequency can be maintained by asserting
COAST.
LPF
45
Passive
PLL Low Pass Filter. Connect recommended PLL filter to LPF pin.
(see Figure 19.)
Sync Stripper
ACS
IN
14
Analog Composite Sync Input. Input to sync stripper with 150mV
threshold.
DCS
OUT
118
Digital Composite Sync Output. Output from sync stripper.
Control
SDA
29
Bi-directional Serial Port Data. Bi-directional data.
SCL
30
Input
Serial Port Clock. Clock input.
A
0
31
Input
Address bit 0. Lower bit of serial port address.
A
1
32
Input
Address bit 1. Upper bit of serial port address.
PWRDN
125
Input
Power Down/Output Control. Powers down the FMS9884A and
tri-states the outputs.
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