2000 Fairchild Semiconductor International
August 2000
Rev. A, August 2000
FQ
AF
4
4
N0
8
QFET
QFET
QFET
QFET
TM
FQAF44N08
80V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as automotive, high
efficiency switching for DC/DC converters, and DC motor
control.
Features
35.6A, 80V, R
DS(on)
= 0.034
@V
GS
= 10 V
Low gate charge ( typical 38 nC)
Low Crss ( typical 90 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
175
C maximum junction temperature rating
Absolute Maximum Ratings
T
C
= 25C unless otherwise noted
Thermal Characteristics
Symbol
Parameter
FQAF44N08
Units
V
DSS
Drain-Source Voltage
80
V
I
D
Drain Current
- Continuous (T
C
= 25C)
35.6
A
- Continuous (T
C
= 100C)
25.2
A
I
DM
Drain Current
- Pulsed
(Note 1)
142.4
A
V
GSS
Gate-Source Voltage
25
V
E
AS
Single Pulsed Avalanche Energy
(Note 2)
450
mJ
I
AR
Avalanche Current
(Note 1)
35.6
A
E
AR
Repetitive Avalanche Energy
(Note 1)
8.3
mJ
dv/dt
Peak Diode Recovery dv/dt
(Note 3)
6.5
V/ns
P
D
Power Dissipation (T
C
= 25C)
83
W
- Derate above 25C
0.56
W/C
T
J
, T
STG
Operating and Storage Temperature Range
-55 to +175
C
T
L
Maximum lead temperature for soldering purposes,
1/8
"
from case for 5 seconds
300
C
Symbol
Parameter
Typ
Max
Units
R
JC
Thermal Resistance, Junction-to-Case
--
1.8
C
/
W
R
JA
Thermal Resistance, Junction-to-Ambient
--
40
C
/
W
! "
!
!
!
"
"
"
! "
!
!
!
"
"
"
S
D
G
TO-3PF
FQAF Series
G
S
D
Rev. A, August 2000
FQAF44N08
(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
2000 Fairchild Semiconductor International
Electrical Characteristics
T
C
= 25C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.49mH, I
AS
= 35.6A, V
DD
= 25V, R
G
= 25
,
Starting T
J
= 25C
3. I
SD
44A, di/dt
300A/
s, V
DD
BV
DSS,
Starting T
J
= 25C
4. Pulse Test : Pulse width
300
s, Duty cycle
2%
5. Essentially independent of operating temperature
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250
A
80
--
--
V
BV
DSS
/
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250
A, Referenced to 25C
--
0.07
--
V/C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 80 V, V
GS
= 0 V
--
--
1
A
V
DS
= 64 V, T
C
= 150C
--
--
10
A
I
GSSF
Gate-Body Leakage Current, Forward
V
GS
= 25 V, V
DS
= 0 V
--
--
100
nA
I
GSSR
Gate-Body Leakage Current, Reverse
V
GS
= -25 V, V
DS
= 0 V
--
--
-100
nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250
A
2.0
--
4.0
V
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= 10 V, I
D
= 17.8 A
--
0.026
0.034
g
FS
Forward Transconductance
V
DS
= 30 V, I
D
= 17.8 A
--
22
--
S
Dynamic Characteristics
C
iss
Input Capacitance
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
--
1100
1430
pF
C
oss
Output Capacitance
--
400
520
pF
C
rss
Reverse Transfer Capacitance
--
90
120
pF
Switching Characteristics
t
d(on)
Turn-On Delay Time
V
DD
= 40 V, I
D
= 44 A,
R
G
= 25
--
15
40
ns
t
r
Turn-On Rise Time
--
170
350
ns
t
d(off)
Turn-Off Delay Time
--
40
90
ns
t
f
Turn-Off Fall Time
--
75
160
ns
Q
g
Total Gate Charge
V
DS
= 64 V, I
D
= 44 A,
V
GS
= 10 V
--
38
50
nC
Q
gs
Gate-Source Charge
--
7.5
--
nC
Q
gd
Gate-Drain Charge
--
18
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current
--
--
35.6
A
I
SM
Maximum Pulsed Drain-Source Diode Forward Current
--
--
142.4
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 35.6 A
--
--
1.5
V
t
rr
Reverse Recovery Time
V
GS
= 0 V, I
S
= 44 A,
dI
F
/ dt = 100 A/
s
--
67
--
ns
Q
rr
Reverse Recovery Charge
--
160
--
nC
FQ
AF
4
4
N0
8
Rev. A, August 2000
2000 Fairchild Semiconductor International
2
4
6
8
10
10
-1
10
0
10
1
10
2
175
25
-55
Notes :
1. V
DS
= 30V
2. 250
s Pulse Test
I
D
,
D
r
ai
n C
u
r
r
e
nt
[
A
]
V
GS
, Gate-Source Voltage [V]
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
10
-1
10
0
10
1
10
2
175
Notes :
1. V
GS
= 0V
2. 250
s Pulse Test
25
I
DR
,
Re
v
e
r
s
e
Dr
a
i
n
Cu
r
r
e
n
t
[
A
]
V
SD
, Source-Drain voltage [V]
0
10
20
30
40
0
2
4
6
8
10
12
V
DS
= 40V
V
DS
= 64V
Note : I
D
= 44A
V
GS
,
G
a
t
e
-
S
our
c
e
V
o
l
t
ag
e [
V
]
Q
G
, Total Gate Charge [nC]
10
-1
10
0
10
1
0
500
1000
1500
2000
2500
3000
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
Notes :
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
C
oss
C
iss
C
apa
ci
t
anc
e [
p
F]
V
DS
, Drain-Source Voltage [V]
0
30
60
90
120
150
180
0.00
0.02
0.04
0.06
0.08
0.10
0.12
Note : T
J
= 25
V
GS
= 20V
V
GS
= 10V
R
D
S
(
on)
[
],
D
r
ai
n
-
S
o
u
r
ce
O
n
-
R
esi
s
t
a
nce
I
D
, Drain Current [A]
10
-1
10
0
10
1
10
0
10
1
10
2
V
GS
Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom : 4.5 V
Notes :
1. 250
s Pulse Test
2. T
C
= 25
I
D
,
D
r
ai
n
C
u
r
r
en
t
[
A
]
V
DS
, Drain-Source Voltage [V]
Typical Characteristics
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
Figure 2. Transfer Characteristics
Figure 1. On-Region Characteristics
2000 Fairchild Semiconductor International
FQAF44N08
Rev. A, August 2000
1 0
- 5
1 0
- 4
1 0
- 3
1 0
- 2
1 0
- 1
1 0
0
1 0
1
1 0
- 2
1 0
- 1
1 0
0
N o t e s :
1 . Z
J C
( t ) = 1 . 8
/ W M a x .
2 . D u t y F a c t o r , D = t
1
/t
2
3 . T
J M
- T
C
= P
D M
* Z
J C
( t )
s i n g l e p u l s e
D = 0 . 5
0 . 0 2
0 . 2
0 . 0 5
0 . 1
0 . 0 1
Z
JC
(
t
)
,
T
her
m
a
l
R
e
s
ponse
t
1
, S q u a r e W a v e P u l s e D u r a t i o n [ s e c ]
25
50
75
100
125
150
175
0
10
20
30
40
I
D
,
D
r
ai
n
C
u
r
r
e
nt
[
A
]
T
C
, Case Temperature [
]
10
0
10
1
10
2
10
-1
10
0
10
1
10
2
10
3
DC
10 ms
1 ms
100
s
Operation in This Area
is Limited by R
DS(on)
Notes :
1. T
C
= 25
o
C
2. T
J
= 175
o
C
3. Single Pulse
I
D
,
D
r
ai
n C
u
r
r
e
nt
[
A
]
V
DS
, Drain-Source Voltage [V]
-100
-50
0
50
100
150
200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes :
1. V
GS
= 10 V
2. I
D
= 22 A
R
DS
(
O
N
)
, (
N
o
r
m
a
liz
e
d
)
D
r
ai
n
-
S
o
u
r
c
e
O
n
-
R
es
i
s
t
a
nc
e
T
J
, Junction Temperature [
o
C]
-100
-50
0
50
100
150
200
0.8
0.9
1.0
1.1
1.2
Notes :
1. V
GS
= 0 V
2. I
D
= 250
A
BV
DSS
,
(
N
or
m
a
l
i
z
ed)
D
r
ai
n-
S
our
c
e
B
r
eak
do
w
n
V
o
l
t
a
g
e
T
J
, Junction Temperature [
o
C]
Typical Characteristics
(Continued)
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Transient Thermal Response Curve
t
1
P
DM
t
2
FQ
AF
4
4
N0
8
Rev. A, August 2000
2000 Fairchild Semiconductor International
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
200nF
12V
Same Type
as DUT
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
200nF
12V
Same Type
as DUT
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
E
AS
=
L I
AS
2
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
10V
DUT
R
G
L
I
D
t
p
E
AS
=
L I
AS
2
----
2
1
E
AS
=
L I
AS
2
----
2
1
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
10V
DUT
R
G
L
L
I
D
I
D
t
p
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
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