www.docs.chipfind.ru
2004 Fairchild Semiconductor Corporation
April 2004
FQD60N03L Rev. B1
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FQD60N03L
N-Channel Logic Level MOSFETs
30V, 30A, 0.023
General Description
This device employs advanced MOSFET technology and
features low gate charge while maintaining low on-
resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Applications
DC/DC converters
Features
Fast switching
r
DS(ON)
= 0.014
(Typ), V
GS
= 10V
r
DS(ON)
= 0.024
(Typ), V
GS
= 4.5V
Q
g
(Typ) = 9.6nC, V
GS
= 5V
Q
gd
(Typ) = 3.4nC
C
ISS
(Typ) = 900pF
MOSFET Maximum Ratings
T
C
=25C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol
Parameter
Ratings
Units
V
DSS
Drain to Source Voltage
30
V
V
GS
Gate to Source Voltage
20
V
I
D
Drain Current
30
A
Continuous (T
C
= 25
o
C, V
GS
= 10V)
Continuous (T
C
= 100
o
C, V
GS
= 4.5V)
19
A
Continuous (T
C
= 25
o
C, V
GS
= 10V, R
JA
= 52
o
C/W)
7.9
A
Pulsed
Figure 4
A
P
D
Power dissipation
Derate above 25
o
C
45
0.37
W
W/
o
C
T
J
, T
STG
Operating and Storage Temperature
-55 to 150
o
C
R
JC
Thermal Resistance Junction to Case TO-252
2.73
o
C/W
R
JA
Thermal Resistance Junction to Ambient TO-252
100
o
C/W
R
JA
Thermal Resistance Junction to Ambient TO-252, 1in
2
copper pad area
52
o
C/W
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FQD60N03L
FQD60N03L
TO-252AA
330mm
16mm
2500 units
D
G
S
TO-252AA
FDD SERIES
GATE
SOURCE
(FLANGE)
DRAIN
2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
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Electrical Characteristics
T
C
= 25C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
(V
GS
= 4.5V)
Switching Characteristics
(V
GS
= 10V)
Unclamped Inductive Switching
Drain-Source Diode Characteristics
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
B
VDSS
Drain to Source Breakdown Voltage
I
D
= 250
A, V
GS
= 0V
30
-
-
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 25V
-
-
1
A
V
GS
= 0V
T
C
= 125
o
C
-
-
250
I
GSS
Gate to Source Leakage Current
V
GS
=
20V
-
-
100
nA
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
A
1
-
3
V
r
DS(ON)
Drain to Source On Resistance
I
D
= 30A, V
GS
= 10V
-
0.014
0.023
I
D
= 19A, V
GS
= 4.5V
-
0.024
0.030
C
ISS
Input Capacitance
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
-
900
-
pF
C
OSS
Output Capacitance
-
210
-
pF
C
RSS
Reverse Transfer Capacitance
-
90
-
pF
Q
g(TOT)
Total Gate Charge at 10V
V
GS
= 0V to 10V
V
DD
= 15V
I
D
= 19A
I
g
= 1.0mA
-
18
28
nC
Q
g(5)
Total Gate Charge at 5V
V
GS
= 0V to 5V
-
9.6
14
nC
Q
g(TH)
Threshold Gate Charge
V
GS
= 0V to 1V
-
1.0
1.5
nC
Q
gs
Gate to Source Gate Charge
-
3.4
-
nC
Q
gd
Gate to Drain "Miller" Charge
-
3.4
-
nC
t
O N
Turn-On Time
V
DD
= 15V, I
D
= 7.9A
V
GS
= 4. 5V, R
GS
= 18
-
-
90
ns
t
d(ON)
Turn-On Delay Time
-
11
-
ns
t
r
Rise Time
-
49
-
ns
t
d(OFF)
Turn-Off Delay Time
-
27
-
ns
t
f
Fall Time
-
28
-
ns
t
OFF
Turn-Off Time
-
-
83
ns
t
O N
Turn-On Time
V
DD
= 15V, I
D
= 7.9A
V
GS
= 10 V, R
GS
= 18
-
-
48
ns
t
d(ON)
Turn-On Delay Time
-
6
-
ns
t
r
Rise Time
-
26
-
ns
t
d(OFF)
Turn-Off Delay Time
-
52
-
ns
t
f
Fall Time
-
28
-
ns
t
OFF
Turn-Off Time
-
-
120
ns
t
AV
Avalanche Time
I
D
= 2.7 A, 3.0 mH
180
-
-
s
V
SD
Source to Drain Diode Voltage
I
SD
= 19A
-
-
1.25
V
I
SD
= 10A
-
-
1.0
V
t
rr
Reverse Recovery Time
I
SD
= 19A, dI
SD
/dt = 100A/
s
-
-
58
ns
Q
RR
Reverse Recovered Charge
I
SD
= 19A, dI
SD
/dt = 100A/
s
-
-
70
nC
2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
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Typical Characteristic
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
T
A
, AMBIENT TEMPERATURE (
o
C)
P
O
W
E
R
D
I
S
S
I
P
A
T
I
O
N
M
U
L
T
I
P
L
I
E
R
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
I
D
,
D
R
A
I
N
C
U
R
R
E
N
T
(
A
)
T
C
, CASE TEMPERATURE (
o
C)
0
10
20
30
40
25
50
75
100
125
150
V
GS
= 10V
V
GS
= 4.5V
0.1
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.01
2
t, RECTANGULAR PULSE DURATION (s)
Z
J
C
,
N
O
R
M
A
L
I
Z
E
D
T
H
E
R
M
A
L
I
M
P
E
D
A
N
C
E
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
I
D
M
,
P
E
A
K
C
U
R
R
E
N
T
(
A
)
t, PULSE WIDTH (s)
20
10
-5
10
-4
10
- 3
10
- 2
10
-1
10
0
10
1
500
T
C
= 25
o
C
I = I
25
150 - T
C
125
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
GS
= 10V
V
GS
= 5V
100
2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
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Figure 5. Transfer Characteristics
Figure 6. Saturation Characteristics
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Typical Characteristic
(Continued)
0
20
40
60
1
2
3
4
5
I
D
,
D
R
A
I
N
C
U
R
R
E
N
T
(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
T
J
= -55
o
C
T
J
= 150
o
C
T
J
= 25
o
C
0
20
40
60
0
0.5
1.0
1.5
2.0
2.5
I
D
,
D
R
A
I
N
C
U
R
R
E
N
T
(
A
)
V
D S
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 4.5V
V
GS
= 10V
V
GS
= 3.5V
V
GS
= 3.0V
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
10
20
30
40
50
2
4
6
8
10
I
D
= 7.9A
V
GS
, GATE TO SOURCE VOLTAGE (V)
r
D
S
(
O
N
)
,
D
R
A
I
N
T
O
S
O
U
R
C
E
O
N
R
E
S
I
S
T
A
N
C
E
(
m
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
I
D
= 30A
0.5
1.0
1.5
2.0
-80
-40
0
40
80
120
160
N
O
R
M
A
L
I
Z
E
D
D
R
A
I
N
T
O
S
O
U
R
C
E
T
J
, JUNCTION TEMPERATURE (
o
C)
O
N
R
E
S
I
S
T
A
N
C
E
V
GS
= 10V, I
D
= 30A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0.4
0.6
0.8
1.0
1.2
1.4
-80
-40
0
40
80
120
160
N
O
R
M
A
L
I
Z
E
D
G
A
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
T
H
R
E
S
H
O
L
D
V
O
L
T
A
G
E
V
GS
= V
DS
, I
D
= 250
A
0.9
1.0
1.1
1.2
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
N
O
R
M
A
L
I
Z
E
D
D
R
A
I
N
T
O
S
O
U
R
C
E
B
R
E
A
K
D
O
W
N
V
O
L
T
A
G
E
I
D
= 250
A
2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
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Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Typical Characteristic
(Continued)
100
1000
0.1
1
10
30
70
2000
C
,
C
A
P
A
C
I
T
A
N
C
E
(
p
F
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
OSS
C
GS
+ C
GD
C
RSS
= C
GD
0
2
4
6
8
10
0
3
6
9
12
15
V
G
S
,
G
A
T
E
T
O
S
O
U
R
C
E
V
O
L
T
A
G
E
(
V
)
Q
g
, GATE CHARGE (nC)
V
DD
= 15V
I
D
= 30A
I
D
= 15A
WAVEFORMS IN
DESCENDING ORDER:
0
20
40
60
80
100
0
10
20
30
40
50
S
W
I
T
C
H
I
N
G
T
I
M
E
(
n
s
)
R
GS
, GATE TO SOURCE RESISTANCE (
)
V
GS
= 4.5V, V
DD
= 15V, I
D
= 7.9A
t
d(OFF)
t
r
t
f
t
d(ON)
S
W
I
T
C
H
I
N
G
T
I
M
E
(
n
s
)
R
GS
, GATE TO SOURCE RESISTANCE (
)
V
GS
= 10V, V
DD
= 15V, I
D
= 7.9A
t
d(OFF)
t
r
t
d(ON)
t
f
0
20
40
60
80
100
120
140
0
10
20
30
40
50
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
t
P
V
GS
0.01
L
I
A S
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
D S
BV
DSS
t
P
I
AS
t
A V
0
2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
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Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
Test Circuits and Waveforms
(Continued)
R
L
V
GS
+
-
V
D S
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
V
GS
= 1V
Q
g(5)
V
GS
= 5V
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
D S
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
D S
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
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Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
J M
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application's ambient
temperature, T
A
(
o
C), and thermal resistance R
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part's current and maximum
power dissipation ratings. Precise determination of P
DM
is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer's preliminary application evaluation. Figure 21
defines the R
JA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
(EQ. 1)
PD M
T
J M
T
A
(
)
R
JA
-----------------------------
=
Area in Inches Squared
(EQ. 2)
RJA
33.32
23.84
0.268 Area
+
(
)
-------------------------------------
+
=
(EQ. 3)
RJA
33.32
154
1.73 Area
+
(
)
----------------------------------
+
=
Area in Centimeters Squared
25
50
75
100
125
0.01
0.1
1
10
Figure 21. Thermal Resistance vs Mounting
Pad Area
R
JA
= 33.32+ 23.84/(0.268+Area) EQ.2
R
J
A
(
o
C
/
W
)
AREA, TOP COPPER AREA in
2
(cm
2
)
R
JA
= 33.32+ 154/(1.73+Area) EQ.3
(0.645)
(6.45)
(64.5)
(0.0645)
2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
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PSPICE Electrical Model
.SUBCKT FQD60N03L 2 1 3 ;
rev June 02
CA 12 8 5.0e-10
CB 15 14 3.9e-10
CIN 6 8 7.8e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 31.0
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 4.53e-9
LSOURCE 3 7 5.38e-10
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.2e-3
RGATE 9 20 2.8
RLDRAIN 2 5 10
RLGATE 1 9 45.3
RLSOURCE 3 7 5.4
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.0e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),3.5))}
.MODEL DBODYMOD D (IS = 3.5e-11 N=1.12 RS = 6.4e-3 TRS1 = 1e-3 TRS2 = 2.0e-6 XTI=2.3CJO = 6.1e-10 T T = 1 e - 8
M=0.62)
.MODEL DBREAKMOD D (RS = 6.0e-1 TRS1 = 1e-3 TRS2 = -8.5e-6)
.MODEL DPLCAPMOD D (CJO = 3.4e-10 IS = 1e-30 N = 10 M = 0.45)
.MODEL MMEDMOD NMOS (VTO = 1.68 KP = 3.5 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.8)
.MODEL MSTROMOD NMOS (VTO = 2.00 KP = 35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.36 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 28 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e-3TC2 = -1e-7)
.MODEL RDRAINMOD RES (TC1 = 3.4e-2 TC2 = 6.0e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -8e-6)
.MODEL RVTEMPMOD RES (TC1 = -2e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 V O N = - 4 . 0 VOFF= -1.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 V O N = - 1 . 5 VOFF= -4.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 V O N = - 0 . 5 VOFF= 0.3)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 V O N = 0 . 3 V O F F = - 0 . 5 )
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
F
Q
D
6
0
N
0
3
L
SABER Electrical Model
REV June 2002
template FQD60N03L n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 3.5e-11, nl=1.12, rs = 6.4e-3, trs1 = 1e-3, trs2 = 2e-6, xti=2.3, cjo = 6.1e-10, tt = 1e-8, m = 0.6 2)
dp..model dbreakmod = (rs = 6e-1, trs1 = 1e-3, trs2 = -8.5e-6)
dp..model dplcapmod = (cjo = 3.4e-10, isl=10e-30, nl=10, m=0.45)
m..model mmedmod = (type=_n, vto = 1.68, kp=3.5, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.00, kp = 35, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.36, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -1.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -4.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5)
c.ca n12 n8 = 5.0e-10
c.cb n15 n14 = 3.9e-10
c.cin n6 n8 = 7.8e-10
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 4.53e-9
l.lsource n3 n7 = 5.38e-10
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -1e-7
res.rdrain n50 n16 = 1.2e-3, tc1 = 3.4e-2, tc2 = 6e-5
res.rgate n9 n20 = 2.8
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 45.3
res.rlsource n3 n7 = 5.4
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1e-2, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -8e-6
spe.ebreak n11 n7 n17 n18 = 31.0
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/120))** 3.5))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
F
Q
D
6
0
N
0
3
L
SPICE Thermal Model
REV June 2002
FQD60N03LT
CTHERM1 th 6 1.3e-3
CTHERM2 6 5 1.5e-3
CTHERM3 5 4 1.6e-3
CTHERM4 4 3 1.7e-3
CTHERM5 3 2 5.8e-3
CTHERM6 2 tl 4.0e-2
RTHERM1 th 6 2.7e-3
RTHERM2 6 5 3.7e-3
RTHERM3 5 4 5.3e-2
RTHERM4 4 3 6.3e-1
RTHERM5 3 2 7.4e-1
RTHERM6 2 tl 7.6e-1
SABER Thermal Model
SABER thermal model FQD60N03LT
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.3e-3
ctherm.ctherm2 6 5 = 1.5e-3
ctherm.ctherm3 5 4 = 1.6e-3
ctherm.ctherm4 4 3 = 1.7e-3
ctherm.ctherm5 3 2 = 5.8e-3
ctherm.ctherm6 2 tl = 4.0e-2
rtherm.rtherm1 th 6 = 2.7e-3
rtherm.rtherm2 6 5 = 3.7e-3
rtherm.rtherm3 5 4 = 5.3e-2
rtherm.rtherm4 4 3 = 6.3e-1
rtherm.rtherm5 3 2 = 7.4e-1
rtherm.rtherm6 2 tl = 7.6e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
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As used herein:
1. Life support devices or systems are devices or
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failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
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changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
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that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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ISOPLANARTM
LittleFETTM
MICROCOUPLERTM
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