2003 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev.1.0.1
Features
Precision Fixed Operating Frequency
FS7M0880(66kHz)
Pulse By Pulse Over Current Limiting
Over Load Protection
Over Voltage Protection (Min. 25V)
Internal Thermal Shutdown Function
Under Voltage Lockout
Internal High Voltage Sense FET
Latch Up Mode
Soft Start
Description
The Fairchild Power Switch(FPS) product family is specially
designed for an off line SMPS with minimal external
components. The Fairchild Power Switch(FPS) consists of a
high voltage power SenseFET and the current mode PWM con-
troller IC. The PWM controller includes an integrated fixed
oscillator, the under voltage lock out, the leading edge blanking
block, the optimized gate turn-on/turn-off driver, the thermal
shut down protection, the over voltage protection, the tempera-
ture compensated precision current sources for loop compensa-
tion and an fault protection circuit. Compared to just PWM
controller combined MosFET or R
CC
switching converter solu-
tion, a Fairchild Power Switch(FPS) can reduce total compo-
nent price, design size, and weight,also simultaneously increase
efficiency, productivity, and system reliability. It has a simple
method of application well suited for cost down design in either
a flyback converter or a forward converter.
TO-3P-5L
1. DRAIN 2. GND 3. V
CC
4. FB 5. S/S
1
Internal Block Diagram
Sense
#4
Feedback
LEB
#5
Soft Start
Rsense
2.5R
R
OSC
Reset
1mA
5uA
Vck
R
S
Q
7.5V
5V
R
S
Q
Voffset
#3 Vcc
Voltage
Ref.
Control IC
SenseFET
#4
Drain
#2
Source
GND
Vcc
Vcc
Reset
Thermal
Protection
UVLO
Good
Logic
OVP
OCL
Sense
#4
Feedback
LEB
#5
Soft Start
Rsense
2.5R
R
OSC
Reset
1mA
5uA
Vck
R
S
Q
7.5V
5V
R
S
Q
Voffset
#3 Vcc
Voltage
Ref.
Control IC
SenseFET
#4
Drain
#2
Source
GND
Vcc
Vcc
Reset
Thermal
Protection
UVLO
Good
Logic
OVP
OCL
FS7M0880
Fairchild Power Switch(FPS)
FS7M0880
2
Absolute Maximum Ratings
Note:
1. T
j
= 25
C to 150
C
2. Repetitive rating: Pulse width limited by maximum junction temperature
3. L = 24mH, V
DD
= 50V, R
G
= 25
, starting Tj =25
C
4. L = 13
H, starting T
j
= 25
C
Parameter
Symbol
Value
Unit
Drain-Gate Voltage (R
GS
=1M
)
V
DGR
800
V
Gate-Source (GND) Voltage
V
GS
30
V
Drain Current Pulsed
(2)
I
DM
32.0
A
DC
Single Pulsed Avalanche Energy
(3)
E
AS
810
mJ
Avalanche Current
(4)
I
AS
15
A
Continuous Drain Current (T
C
=25
C)
I
D
8.0
A
DC
Continuous Drain Current (T
C
=100
C)
I
D
5.6
A
DC
Maximum Supply Voltage
V
CC,MAX
30
V
Input Voltage Range
V
FB
-0.3 to V
SD
V
Total Power Dissipation
P
D
190
W
Derating
1.54
W/
C
Operating Ambient Temperature
T
A
-25 to +85
C
Storage Temperature
T
STG
-55 to +150
C
FS7M0880
3
Electrical Characteristics (SFET part)
(Ta=25
C unless otherwise specified)
Note:
1. Pulse test: Pulse width
300
S, duty cycle
2%
2.
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Drain-Source Breakdown Voltage
BV
DSS
V
GS
=0V, I
D
=50
A
800
-
-
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
=Max., Rating,
V
GS
=0V
-
-
50
A
V
DS
=0.8Max., Rating,
V
GS
=0V, T
C
=125
C
-
-
200
A
Static Drain-Source On Resistance
(note1)
R
DS(ON)
V
GS
=10V, I
D
=5.0A
-
1.2
1.5
Forward Transconductance
(note1)
gfs
V
DS
=15V, I
D
=5.0A
1.5
2.5
-
S
Input Capacitance
Ciss
V
GS
=0V, V
DS
=25V,
f=1MHz
-
2460
-
pF
Output Capacitance
Coss
-
210
-
Reverse Transfer Capacitance
Crss
-
64
-
Turn On Delay Time
td(on)
V
DD
=0.5BV
DSS
, I
D
=8.0A
(MOSFET switching
time are essentially
independent of
operating temperature)
-
-
90
nS
Rise Time
tr
-
95
200
Turn Off Delay Time
td(off)
-
150
450
Fall Time
tf
-
60
150
Total Gate Charge
(Gate-Source+Gate-Drain)
Qg
V
GS
=10V, I
D
=8.0A,
V
DS
=0.5BV
DSS
(MOSFET
switching time are
essentially independent of
operating temperature)
-
-
150
nC
Gate-Source Charge
Qgs
-
20
-
Gate-Drain (Miller) Charge
Qgd
-
70
-
S
1
R
----
=
FS7M0880
4
Electrical Characteristics (CONTROL part)
(Continued)
(Ta=25
C unless otherwise specified)
Note:
1. These parameters, although guaranteed, are not 100% tested in production
2. These parameters, although guaranteed, are tested in EDS (wafer test) process
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
UVLO SECTION
Start Threshold Voltage
V
START
-
14
15
16
V
Stop Threshold Voltage
V
STOP
After turn on
8
9
10
V
OSCILLATOR SECTION
Initial Frequency
F
OSC
-
60
66
72
kHz
Frequency Change With Temperature
(2)
F/
T
-25
C
Ta
+85
C
-
5
10
%
Maximum Duty Cycle
Dmax
-
45
50
55
%
FEEDBACK SECTION
Feedback Source Current
I
FB
Ta=25
C, 0V
Vfb
3V
0.7
0.9
1.1
mA
Shutdown Delay Current
Idelay
Ta=25
C, 5V
Vfb
V
SD
4.0
5.0
6.0
A
SOFT START SECTION
Soft Start Voltage
V
SS
V
FB
=2V
4.7
5.0
5.3
V
Soft Start Current
I
SS
Sync & S/S=GND
0.8
1.0
1.2
mA
REFERENCE SECTION
Output Voltage
(1)
Vref
Ta=25
C
4.80
5.00
5.20
V
Temperature Stability
(1)(2)
Vref/
T
-25
C
Ta
+85
C
-
0.3
0.6
mV/
C
CURRENT LIMIT (SELT-PROTECTION)SECTION
Peak Current Limit
I
OVER
Max. inductor current
4.40
5.00
5.60
A
PROTECTION SECTION
Thermal Shutdown Temperature (Tj)
(1)
T
SD
-
140
C
Over Voltage Protection Voltage
V
OVP
-
25
28
31
V
Over Current Protection Voltage
V
OCP
-
1.05
1.10
1.15
V
TOTAL DEVICE SECTION
Start Up Current
I
START
V
CC
=14V
-
40
80
uA
Operating Supply Current
(Control Part Only)
I
OP
Ta=25
C
-
8
12
mA
Iop(lat)
After latch,
Vcc=Vstop-0.1V
150
250
350
uA
Shutdown Feedback Voltage
V
SD
-
6.9
7.5
8.1
V
FS7M0880
5
Block Diagram
It can be divided into several large, functional sections:
under voltage lockout circuitry (UVLO); reference voltage;
oscillator (OSC); pulse width modulation (PWM) block;
protection circuits; and gate driving circuits.
Start Up
Input voltage range: 85 ~ 265 V (AC)
When Vac is minimum and it is started by the DC Link bulk
capacitor, the starting resistance is calculated as follows:
When Vac is maximum and it is started by the DC Link Bulk
capacitor, the power loss is calculated as follows:
When it is started by the one-phase of the AC-Lines and Vac
is minimum, the starting resistance is calculated as follows:
When it is started bythe one-phase of the AC_Line and Vac
is maximum, the power loss is calculated as follows:
The starting current across the starting resistor charges the
SPS V
CC
capacitor. When the V
CC
becomes greater than the
starting voltage, the SPS starts to switch the built-in
MOSFET. Once it starts, the current in the SPS control IC
abruptly is increased to 7mA, makes it difficult to operate
with the current through the starting resistor. Therefore, after
it starts, the auxiliary winding of the transformer supplies
most of the power to SPS. It is best to use an appropriate size
V
CC
power capacitor, generally about 33
F, because if it is
too large, the starting time can be delayed. This operation is
described in Fig 2. Although V
CC
only needs to be set above
9V during operation, it should be set such that OVP does not
execute during an overload condition. For a full load, about
18~20V is appropriate for the V
CC
voltage and for no load,
about 13~14V.
Protection
The FPS has several self-protection circuits, which can
operate without additional external components, thereby
acquiring reliability without increase in cost. After a
protection circuit comes on, it can completely stop the SMPS
until the cutoff AC power is reconnected (Latch Mode
Protection) or it can make the SMPS operate above the
UVLO by unlatching the control voltage below the ULVO
(Auto Restart Mode Protection).
These two operations are user-command operations, so the
user can select the
operation from the IC or by carefully controlling circuit
constants. The operation and applications for each protection
are described below.
Figure 2. Start-up Waveform
Over Load Protection
In abnormal status of SMPS over load is distinguished from
load short. This happens when a load exceeds a pre-set load
during normal operation. That is, the FPS overload
protection circuit stops the FPS if an instantaneous load
increases and becomes greater than 50W during normal
operation, when the maximum SMPS output had been
pre-set to 30W. In this type of protection, the protection
Rstart
85 2 15
80
A
---------------------------
1.3M
=
=
Ploss
265 2 15
(
)
2
1.3M
--------------------------------------
0.1 W
( )
=
=
265V
85V
Va
RStart
2 85
2 15
2
----------------------------------------
80
A
(
)
=
38M
=
Va rms
(
)
1
2
------
Vp
t
sin
15
(
)
2
dt
o
=
177V Vp
265 2
=
(
)
=
Ploss
Va rms
(
)
2
Rstart
---------------------------
177
(
)
2
38M
------------------
=
=
82 mW
(
)
=
Figure 1. Detail of the undervoltage lockout (UVLO)
circuitry in a Fairchild Power Switch. The gate
operating circuit holds in a low state during UVL
thereby maintaining the SenseFET at turnoff.
UVLO
UVLO
UVLO
UVLO
Fig 2
< Start-up Waveform >
Vcc
Vz
15V
9V
20
Icc
[mA]
[V]
0.1
6V
Power On Reset
Range
7
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