2002 Fairchild Semiconductor Corporation
Rev. A1, December 2002
I
R
F
6
50B /
I
R
FS650B
IRF650B / IRFS650B
200V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters,
switch mode power supplies, DC-AC converters for
uninterrupted power supply and motor control.
Features
28A, 200V, R
DS(on)
= 0.085
@V
GS
= 10 V
Low gate charge ( typical 95 nC)
Low Crss ( typical 75 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Absolute Maximum Ratings
T
C
= 25C unless otherwise noted
* Drain current limited by maximum junction temperature.
Thermal Characteristics
Symbol
Parameter
IRF650B
IRFS650B
Units
V
DSS
Drain-Source Voltage
200
V
I
D
Drain Current
- Continuous (T
C
= 25C)
28
28 *
A
- Continuous (T
C
= 100C)
17.7
17.7 *
A
I
DM
Drain Current
- Pulsed
(Note 1)
112
112
A
V
GSS
Gate-Source Voltage
30
V
E
AS
Single Pulsed Avalanche Energy
(Note 2)
600
mJ
I
AR
Avalanche Current
(Note 1)
28
A
E
AR
Repetitive Avalanche Energy
(Note 1)
15.6
mJ
dv/dt
Peak Diode Recovery dv/dt
(Note 3)
5.5
V/ns
P
D
Power Dissipation (T
C
= 25C)
156
50
W
- Derate above 25C
1.25
0.4
W/C
T
J
, T
STG
Operating and Storage Temperature Range
-55 to +150
C
T
L
Maximum lead temperature for soldering purposes,
1/8
"
from case for 5 seconds
300
C
Symbol
Parameter
IRF650B
IRFS650B
Units
R
JC
Thermal Resistance, Junction-to-Case Max.
0.8
2.51
C
/
W
R
CS
Thermal Resistance, Case-to-Sink Typ.
0.5
--
C
/
W
R
JA
Thermal Resistance, Junction-to-Ambient Max
62.5
62.5
C
/
W
TO-220
IRF Series
G
S
D
S
D
G
TO-220F
IRFS Series
G
S
D
Rev. A1, December 2002
I
R
F
6
50B /
I
R
FS650B
(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
2002 Fairchild Semiconductor Corporation
Electrical Characteristics
T
C
= 25C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 1.15mH, I
AS
= 28A, V
DD
= 50V, R
G
= 25
,
Starting T
J
= 25C
3. I
SD
32A, di/dt
300A/
s, V
DD
BV
DSS,
Starting T
J
= 25C
4. Pulse Test : Pulse width
300
s, Duty cycle
2%
5. Essentially independent of operating temperature
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250
A
200
--
--
V
BV
DSS
/
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250
A, Referenced to 25C
--
0.2
--
V/C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 200 V, V
GS
= 0 V
--
--
10
A
V
DS
= 160 V, T
C
= 125C
--
--
100
A
I
GSSF
Gate-Body Leakage Current, Forward
V
GS
= 30 V, V
DS
= 0 V
--
--
100
nA
I
GSSR
Gate-Body Leakage Current, Reverse
V
GS
= -30 V, V
DS
= 0 V
--
--
-100
nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250
A
2.0
--
4.0
V
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= 10 V, I
D
= 14 A
--
0.071
0.085
g
FS
Forward Transconductance
V
DS
= 40 V, I
D
= 14 A
--
25
--
S
Dynamic Characteristics
C
iss
Input Capacitance
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
--
2600
3400
pF
C
oss
Output Capacitance
--
330
430
pF
C
rss
Reverse Transfer Capacitance
--
75
100
pF
Switching Characteristics
t
d(on)
Turn-On Delay Time
V
DD
= 100 V, I
D
= 32 A,
R
G
= 25
--
30
70
ns
t
r
Turn-On Rise Time
--
240
490
ns
t
d(off)
Turn-Off Delay Time
--
295
600
ns
t
f
Turn-Off Fall Time
--
195
400
ns
Q
g
Total Gate Charge
V
DS
= 160 V, I
D
= 32 A,
V
GS
= 10 V
--
95
123
nC
Q
gs
Gate-Source Charge
--
13
--
nC
Q
gd
Gate-Drain Charge
--
43
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current
--
--
28
A
I
SM
Maximum Pulsed Drain-Source Diode Forward Current
--
--
112
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 28 A
--
--
1.5
V
t
rr
Reverse Recovery Time
V
GS
= 0 V, I
S
= 32 A,
dI
F
/ dt = 100 A/
s
--
220
--
ns
Q
rr
Reverse Recovery Charge
--
1.89
--
C
Rev. A1, December 2002
2002 Fairchild Semiconductor Corporation
I
R
F
6
50B /
I
R
FS650B
0
20
40
60
80
100
0
2
4
6
8
10
12
V
DS
= 100V
V
DS
= 40V
V
DS
= 160V
Note : I
D
= 32 A
V
GS
,
G
a
t
e
-
S
our
c
e
V
o
l
t
age [
V
]
Q
G
, Total Gate Charge [nC]
10
-1
10
0
10
1
0
2000
4000
6000
8000
C
oss
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
Notes :
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
C
iss
C
apa
c
i
t
a
nc
e [
p
F]
V
DS
, Drain-Source Voltage [V]
0
30
60
90
120
0.0
0.1
0.2
0.3
0.4
V
GS
= 20V
V
GS
= 10V
Note : T
J
= 25
R
DS
(
O
N)
[
],
D
r
ai
n-
S
o
u
r
c
e
O
n
-
R
es
i
s
t
anc
e
I
D
, Drain Current [A]
2
4
6
8
10
10
-1
10
0
10
1
10
2
150
o
C
25
o
C
-55
o
C
Notes :
1. V
DS
= 40V
2. 250
s Pulse Test
I
D
,
D
r
ai
n C
u
r
r
e
nt
[
A
]
V
GS
, Gate-Source Voltage [V]
10
-1
10
0
10
1
10
0
10
1
10
2
V
GS
Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
Bottom : 5.0 V
Notes :
1. 250
s Pulse Test
2. T
C
= 25
I
D
,
D
r
a
i
n C
u
r
r
ent
[
A
]
V
DS
, Drain-Source Voltage [V]
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
10
0
10
1
10
2
150
Notes :
1. V
GS
= 0V
2. 250
s Pulse Test
25
I
DR
,
R
e
v
e
r
s
e D
r
ai
n C
u
r
r
e
nt
[
A
]
V
SD
, Source-Drain voltage [V]
Typical Characteristics
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
Figure 2. Transfer Characteristics
Figure 1. On-Region Characteristics
2002 Fairchild Semiconductor Corporation
Rev. A1, December 2002
I
R
F
6
50B /
I
R
FS650B
10
0
10
1
10
2
10
-2
10
-1
10
0
10
1
10
2
10
3
100
s
1 ms
DC
100 ms
10 ms
Operation in This Area
is Limited by R
DS(on)
Notes :
1. T
C
= 25
o
C
2. T
J
= 150
o
C
3. Single Pulse
I
D
,
D
r
ai
n C
u
r
r
e
nt
[
A
]
V
DS
, Drain-Source Voltage [V]
25
50
75
100
125
150
0
5
10
15
20
25
30
I
D
,
D
r
ai
n C
u
r
r
e
nt
[
A
]
T
C
, Case Temperature [
]
10
0
10
1
10
2
10
-1
10
0
10
1
10
2
10
s
DC
10 ms
1 ms
100
s
Operation in This Area
is Limited by R
DS(on)
Notes :
1. T
C
= 25
o
C
2. T
J
= 150
o
C
3. Single Pulse
I
D
,
D
r
ai
n C
u
r
r
e
nt
[
A
]
V
DS
, Drain-Source Voltage [V]
-100
-50
0
50
100
150
200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes :
1. V
GS
= 10 V
2. I
D
= 16 A
R
DS
(
O
N
)
,
(
N
or
m
a
l
i
z
ed)
D
r
ai
n-
Sour
c
e
O
n
-
R
es
i
s
t
a
n
c
e
T
J
, Junction Temperature [
o
C]
-100
-50
0
50
100
150
200
0.8
0.9
1.0
1.1
1.2
Notes :
1. V
GS
= 0 V
2. I
D
= 250
A
BV
DS
S
,
(
N
o
r
m
a
liz
e
d
)
D
r
a
i
n-
S
o
ur
c
e
B
r
ea
k
d
o
w
n
V
o
l
t
ag
e
T
J
, Junction Temperature [
o
C]
Typical Characteristics
(Continued)
Figure 9-1. Maximum Safe Operating Area
for IRF650B
Figure 10. Maximum Drain Current
vs Case Temperature
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
Figure 9-2. Maximum Safe Operating Area
for IRFS650B
Rev. A1, December 2002
2002 Fairchild Semiconductor Corporation
I
R
F
6
50B /
I
R
FS650B
Typical Characteristics
(Continued)
1 0
-5
1 0
-4
1 0
-3
1 0
-2
1 0
-1
1 0
0
1 0
1
1 0
-2
1 0
-1
1 0
0
N o te s :
1 . Z
J C
(t) = 0 .8
/W M a x .
2 . D u ty F a c to r, D = t
1
/t
2
3 . T
J M
- T
C
= P
D M
* Z
J C
(t)
s in g le p u ls e
D = 0 .5
0 . 0 2
0 . 2
0 . 0 5
0 . 1
0 . 0 1
Z
JC
(t), T
h
e
r
m
a
l
R
e
s
p
o
n
s
e
t
1
, S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve for IRF650B
t
1
P
DM
t
2
1 0
-5
1 0
-4
1 0
-3
1 0
-2
1 0
-1
1 0
0
1 0
1
1 0
-2
1 0
-1
1 0
0
N o te s :
1 . Z
J C
(t) = 2 .5 1
/W M a x .
2 . D u ty F a c to r, D = t
1
/t
2
3 . T
J M
- T
C
= P
D M
* Z
J C
(t)
s in g le p u ls e
D = 0 .5
0 .0 2
0 .2
0 .0 5
0 .1
0 .0 1
Z
JC
(t), T
h
e
r
m
a
l
R
e
s
p
o
n
s
e
t
1
, S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve for IRFS650B
t
1
P
DM
t
2
Rev. A1, December 2002
2002 Fairchild Semiconductor Corporation
I
R
F
6
50B /
I
R
FS650B
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
200nF
12V
Same Type
as DUT
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
200nF
12V
Same Type
as DUT
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
E
AS
=
L I
AS
2
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
10V
DUT
R
G
L
I
D
t
p
E
AS
=
L I
AS
2
----
2
1
E
AS
=
L I
AS
2
----
2
1
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
10V
DUT
R
G
L
L
I
D
I
D
t
p
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
2002 Fairchild Semiconductor Corporation
Rev. A1, December 2002
I
R
F
6
50B /
I
R
FS650B
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
dv/dt controlled by R
G
I
SD
controlled by pulse period
V
DD
L
I
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
I
FM
, Body Diode Forward Current
Body Diode Reverse Current
I
RM
Body Diode Recovery dv/dt
di/dt
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
dv/dt controlled by R
G
I
SD
controlled by pulse period
V
DD
L
L
I
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
I
FM
, Body Diode Forward Current
Body Diode Reverse Current
I
RM
Body Diode Recovery dv/dt
di/dt
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
Rev. A1, December 2002
2002 Fairchild Semiconductor Corporation
I
R
F
6
50B /
I
R
FS650B
Package Dimensions
4.50
0.20
9.90
0.20
1.52
0.10
0.80
0.10
2.40
0.20
10.00
0.20
1.27
0.10
3.60
0.10
(8.70)
2.80
0.10
15.90
0.20
10.08
0.30
18.95MAX.
(1.70)
(3.70)
(3.00)
(1.46)
(1.00)
(45
)
9.20
0.20
13.08
0.20
1.30
0.10
1.30
+0.10
0.05
0.50
+0.10
0.05
2.54TYP
[2.54
0.20
]
2.54TYP
[2.54
0.20
]
TO-220
Dimensions in Millimeters
Rev. A1, December 2002
2002 Fairchild Semiconductor Corporation
I
R
F
6
50B /
I
R
FS650B
Package Dimensions
(Continued)
(7.00)
(0.70)
MAX1.47
(30
)
#1
3.30
0.10
15.80
0.20
15.87
0.20
6.68
0.20
9.75
0.30
4.70
0.20
10.16
0.20
(1.00x45
)
2.54
0.20
0.80
0.10
9.40
0.20
2.76
0.20
0.35
0.10
3.18
0.10
2.54TYP
[2.54
0.20
]
2.54TYP
[2.54
0.20
]
0.50
+0.10
0.05
TO-220F
Dimensions in Millimeters
2002 Fairchild Semiconductor Corporation
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I1
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intended to be an exhaustive list of all such trademarks.
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2
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