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Электронный компонент: IRFD120

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2002 Fairchild Semiconductor Corporation
IRFD120 Rev. B
IRFD120
1.3A, 100V, 0.300 Ohm, N-Channel
Power MOSFET
This advanced power MOSFET is designed, tested, and
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. These are
N-Channel enhancement mode silicon gate power field
effect transistors designed for applications such as switching
regulators, switching convertors, motor drivers, relay drivers,
and drivers for high power bipolar switching transistors
requiring high speed and low gate drive power. They can be
operated directly from integrated circuits.
Formerly developmental type TA17401.
Features
1.3A, 100V
r
DS(ON)
= 0.300
Single Pulse Avalanche Energy Rated
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Related Literature
- TB334 "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
HEXDIP
Ordering Information
PART NUMBER
PACKAGE
BRAND
IRFD120
HEXDIP
IRFD120
NOTE: When ordering, use the entire part number.
G
D
S
SOURCE
GATE
DRAIN
Data Sheet
January 2002
2002 Fairchild Semiconductor Corporation
IRFD120 Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
IRFD120
UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
100
V
Drain to Gate Voltage (R
GS
= 20k
)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
100
V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
1.3
A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
5.2
A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
20
V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
1.0
W
Linear Derating Factor (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.008
W/
o
C
Single Pulse Avalanche Energy Rating (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
36
mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V (Figure 9)
100
-
-
V
Gate Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A
2.0
-
4.0
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= Rated BV
DSS
, V
GS
= 0V
-
-
25
A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
J
= 125
o
C
-
-
250
A
On-State Drain Current (Note 2)
I
D(ON)
V
DS
> I
D(ON)
x r
DS(ON)
Max, V
GS
= 10V
1.3
-
-
A
Gate Source Leakage
I
GSS
V
GS
=
20V
-
-
500
nA
Drain Source On Resistance (Note 2)
r
DS(ON)
I
D
= 0.6A, V
GS
= 10V (Figures 7, 8)
-
0.25
0.30
Forward Transconductance (Note 2)
gfs
V
DS
> I
D(ON)
x r
DS(ON)MAX
, I
D
= 0.6A (Figure 11)
0.9
1.0
-
S
Turn-On Delay Time
t
d(ON)
V
DD
= 0.5 x Rated BV
DSS
, I
D
1.3A,
V
GS
= 10V, R
G
= 9.1
R
L
= 38.5
for V
DD
= 50V
MOSFET Switching Times are Essentially
Independent of Operating Temperature
-
20
40
ns
Rise Time
t
r
-
35
70
ns
Turn-Off Delay Time
t
d(OFF)
-
50
100
ns
Fall Time
t
f
-
35
70
ns
Total Gate Charge
(Gate to Source + Gate to Drain)
Q
g(TOT)
V
GS
= 10V, I
D
= 1.3A, V
DS
= 0.8 x Rated BV
DSS
,
I
g(REF)
= 1.5mA (Figure 13)
Gate Charge is Essentially Independent of Operating
Temperature
-
11
15
nC
Gate to Source Charge
Q
gs
-
6.0
-
nC
Gate to Drain "Miller" Charge
Q
gd
-
5.0
-
nC
Input Capacitance
C
ISS
V
GS
= 0V, V
DS
= 25V, f = 1MHz (Figure 10)
-
450
-
pF
Output Capacitance
C
OSS
-
200
-
pF
Reverse Transfer Capacitance
C
RSS
-
50
-
pF
Internal Drain Inductance
L
D
Measured From the Drain
Lead, 2mm (0.08in) from
Package to Center of Die
Modified MOSFET
Symbol Showing the
Internal Device's
Inductances
-
4.0
-
nH
Internal Source Inductance
L
S
Measured From the Source
Lead, 2mm (0.08in) from
Header to Source Bonding
Pad
-
6.0
-
nH
Thermal Resistance Junction to Ambient
R
JA
Free Air Operation
-
-
120
o
C/W
L
S
L
D
G
D
S
IRFD120
2002 Fairchild Semiconductor Corporation
IRFD120 Rev. B
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Continuous Source to Drain Current
I
SD
Modified MOSFET Symbol
Showing the Integral
Reverse P-N Junction
Diode
-
-
1.3
A
Pulse Source to Drain Current
I
SDM
-
-
5.2
A
Source to Drain Diode Voltage (Note 2)
V
SD
T
J
= 25
o
C, I
SD
= 1.3A, V
GS
= 0V (Figure 12)
-
-
2.5
V
Reverse Recovery Time
t
rr
T
J
= 150
o
C, I
SD
= 1.3A, dI
SD
/dt = 100A/
s
-
280
-
ns
Reverse Recovery Charge
Q
RR
T
J
= 150
o
C, I
SD
= 1.3A, dI
SD
/dt = 100A/
s
-
1.6
-
C
NOTES:
2. Pulse test: pulse width
300
s, duty cycle
2%.
3. V
DD
= 25V, starting T
J
= 25
o
C, L = 32mH, R
G
= 25
,
peak I
AS
= 1.3A.
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. OUTPUT CHARACTERISTICS
G
D
S
T
A
, AMBIENT TEMPERATURE (
o
C)
PO
WER DISSIP
A
TION MUL
TIPLIER
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
T
A
, AMBIENT TEMPERATURE (
o
C)
50
75
100
25
150
1.5
1.2
0.9
0
0.6
I
D,
DRAIN CURRENT (A)
0.3
125
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1
I
D
,
DRAIN CURRENT (A)
100
0.1
10
0.1
0.01
10
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
T
J
= MAX RATED
1ms
10ms
100ms
100
s
DC
1
I
D
,
DRAIN CURRENT (A)
0
10
20
30
40
4
8
12
16
20
50
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0
V
GS
= 4V
V
GS
= 5V
V
GS
= 7V
PULSE DURATION = 80
s
V
GS
= 10V
V
GS
= 8V
V
GS
= 6V
V
GS
= 9V
DUTY CYCLE = 0.5% MAX
IRFD120
2002 Fairchild Semiconductor Corporation
IRFD120 Rev. B
FIGURE 5. SATURATION CHARACTERISTICS
FIGURE 6. TRANSFER CHARACTERISTICS
NOTE:
Heating effect of 2
s pulse is minimal.
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Typical Performance Curves
Unless Otherwise Specified (Continued)
I
D
,
DRAIN CURRENT (A)
0
1
2
3
4
2
4
6
8
10
5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0
V
GS
= 9V
V
GS
= 4V
V
GS
= 5V
V
GS
= 6V
V
GS
= 10V
V
GS
= 8V
V
GS
= 7V
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
20
I
DS(ON)
,
DRAIN
T
O
SOURCE CURRENT (A)
V
GS
, GATE TO SOURCE VOLTAGE (V)
16
12
8
0
8
6
4
2
0
10
4
T
J
= 25
o
C
T
J
= 125
o
C
T
J
= -55
o
C
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DS
> I
D(ON)
x r
DS(ON)MAX
0
0.4
0.8
10
20
30
r
DS(ON)
,
DRAIN
T
O
SOURCE
I
D
, DRAIN CURRENT (A)
40
0
0.2
0.6
V
GS
= 10V
V
GS
= 20V
ON RESIST
ANCE (
)
2
s PULSE TEST
NORMALIZED DRAIN
T
O
SOURCE
2.2
1.4
1.0
0.6
0.2
40
T
J
, JUNCTION TEMPERATURE (
o
C)
120
160
1.8
80
0
-40
ON RESIST
ANCE
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
GS
= 10V, I
D
= 0.6A
1.25
0.95
0.85
0.75
-40
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN
T
O
SOURCE
BREAKDO
WN V
O
L
T
A
G
E
160
1.05
1.15
0
40
80
120
I
DS
= 250
A
1000
200
0
0
20
50
C,
CAP
A
CIT
ANCE (pF)
600
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
800
400
10
30
C
ISS
C
OSS
C
RSS
40
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
IRFD120
2002 Fairchild Semiconductor Corporation
IRFD120 Rev. B
FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified (Continued)
I
D
, DRAIN CURRENT (A)
g
fs
,
TRANSCONDUCT
ANCE
(S)
0
4
8
12
16
1
2
3
4
5
20
0
T
J
= -55
o
C
T
J
= 25
o
C
T
J
= 125
o
C
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0
2
3
0.1
10
2
I
SD
,
SOURCE
T
O
DRAIN CURRENT (A)
V
SD
, SOURCE TO DRAIN VOLTAGE (V)
10
2
1
5
5
2
4
T
J
= 25
o
C
T
J
= 150
o
C
2
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
Q
G
, GATE CHARGE (nC)
V
GS
,
GA
TE
T
O
SOURCE (V)
0
4
6
10
5
15
20
I
D
= 5.2A
10
0
2
8
V
DS
= 80V
V
DS
= 50V
V
DS
= 20V
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
IRFD120
2002 Fairchild Semiconductor Corporation
IRFD120 Rev. B
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms
(Continued)
V
GS
R
L
R
G
DUT
+
-
V
DD
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
0.3
F
12V
BATTERY
50k
V
DS
S
DUT
D
G
I
g(REF)
0
(ISOLATED
V
DS
0.2
F
CURRENT
REGULATOR
I
D
CURRENT
SAMPLING
I
G
CURRENT
SAMPLING
SUPPLY)
RESISTOR
RESISTOR
SAME TYPE
AS DUT
Q
g(TOT)
Q
gd
Q
gs
V
DS
0
V
GS
V
DD
I
g(REF)
0
IRFD120
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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