www.fairchildsemi.com
REV. 1.1.3 3/8/02
Features
Can source and sink up to 3A, no heat sink required
Integrated Power MOSFETs
Generates termination voltages for DDR SDRAM,
SSTL-2 SDRAM, SGRAM, or equivalent memories
Generates termination voltages for active termination
schemes for DDR SDRAM, GTL+, Rambus, VME,
LV-TTL, HSTL, PECL and other high speed logic
V
REF
input available for external voltage divider
Separate voltages for V
CCQ
and PV
DD
Buffered V
REF
output
V
OUT
of 3% or less at 3A
Minimum external components
Shutdown for standby or suspend mode operation
0 to +70C and -40 to +85C temperature ranges
available
Thermal Shutdown
130C
Description
The ML6554 switching regulator is designed to convert volt-
age supplies ranging from 2.3V to 4V into a desired output
voltage or termination voltage for various applications. The
ML6554 can be implemented to produce regulated output
voltages in two different modes. In the default mode, when
the V
REF
pin is open, the ML6554 output voltage is 50% of
the voltage applied to V
CCQ
. The ML6554 can also be used
to produce various user-defined voltages by forcing a voltage
on the VREF
IN
pin. In this case, the output voltage follows
the input VREF
IN
voltage. The switching regulator is capa-
ble of sourcing or sinking up to 3A of current while regulat-
ing an output V
TT
voltage to within 3% or less.
The ML6554, used in conjunction with series termination
resisitors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs. The voltage output of the regulator can
be used as a termination voltage for other bus interface
standards such as DDR SDRAM, SSTL, CMOS, Rambus
TM
,
GTL+, VME, LV-CMOS, LV-TTL, HSTL and PECL.
Block Diagram
VL2
AGND
13
VREFIN
VREFOUT
11
6
VDD
1
SHDN
12
PVDD2
PVDD1
7
VL1
3
+
+
AVCC
VCCQ
15
OSCILLATOR/
RAMP
GENERATOR
S
R
Q
Q
(VOUT)
(VOUT)
PGND1
DGND
VFB
PGND2
2
4
5
8
VDD
9
14
10
VREF BUFFER
ERROR AMP
RAMP
COMPARATOR
+
16
200k
200k
ML6554
3A Bus Termination Regulator
ML6554
PRODUCT SPECIFICATION
2
REV. 1.1.3 3/8/02
Pin Configuration
Pin Description
Pin
Name
Function
1
V
DD
Digital supply voltage
2
PV
DD1
Voltage supply for internal power transistors
3
V
L1
Output voltage/ inductor connection
4
P
GND1
Ground for output power transistors
5
P
GND2
Ground for output power transistors
6
V
L2
Output voltage/inductor connection
7
PV
DD2
Voltage supply for internal power transistors
8
D
GND
Digital ground
9
V
DD
Digital supply voltage
10
V
FB
Input for external compensation feedback
11
VREF
IN
Input for external reference voltage
12
SHDN
Shutdown active low. CMOS input level
13
AGND
Ground for internal reference voltage divider
14
VREF
OUT
Reference voltage output
15
V
CCQ
Voltage reference for internal voltage divider
16
AV
CC
Analog voltage supply
ML6554
16-Pin PSOP (U16)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
PRODUCT SPECIFICATION
ML6554
REV. 1.1.3 3/8/02
3
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Operating Conditions
Electrical Characteristics
Unless otherwise specified, AV
CC
= V
DD
= PV
DD
= 3.3V 10%, TA = Operating Temperature Range (Note 1)
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Infinite heat sink
Parameter
Min.
Max.
Units
PV
DD
4.5
V
Voltage on Any Other Pin
GND 0.3
V
IN
+ 0.3
V
Average Switch Current (I
AVG
)
3.0
A
Junction Temperature
150
C
Storage Temperature Range
-65
150
C
Lead Temperature (Soldering, 10 sec)
150
C
Thermal Resistance (
JC
)(Note 2)
2
C/W
Output Current, Source or Sink
3.0
A
Parameter
Min.
Max.
Units
Temperature Range, CU suffix
0
70
C
Temperature Range, IU suffix
-40
+85
C
PV
DD
Operating Range
2.0
4.0
V
V
CCQ
Operating Range
1.4
4.0
V
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
Switching Regulator
V
TT
Output Voltage, SSTL_2
(See Figure 1)
I
OUT
= 0,
V
REF
= open
V
CCQ
= 2.3V
1.12
1.15
1.18
V
V
CCQ
= 2.5V
1.22
1.25
1.28
V
V
CCQ
= 2.7V
1.32
1.35
1.38
V
I
OUT
= 3A,
V
REF
= open
V
CCQ
= 2.3V
1.09
1.15
1.21
V
V
CCQ
= 2.5V
1.19
1.25
1.31
V
V
CCQ
= 2.7V
1.28
1.35
1.42
V
VREF
OUT
Internal Resistor Divider
I
OUT
= 0
V
CCQ
= 2.3V 1.139
1.15
1.162
V
V
CCQ
= 2.5V 1.238
1.25
1.263
V
V
CCQ
= 2.7V 1.337
1.35
1.364
V
Z
IN
V
REF
Reference Pin Input
Impedance
V
CCQ
= 0
100
k
Switching Frequency
650
kHz
V
OFFSET
Offset Voltage V
TT
VREF
OUT
AV
CC
= 2.5V No Load V
CCQ
= 2.5
20
20
mV
Supply
I
Q
Quiescent Current
I
OUT
= 0, no load
V
CCQ
= 2.5V
I
VCCQ
6
10
A
I
AVCC
0.5
1.0
mA
I
AVCC
SD
0.2
0.5
mA
I
VDD
0.25
1.0
mA
I
VDD
SD
0.2
1.0
mA
I
PVDD
100
250
A
Buffer
I
REF
Output Load Current
3
mA
ML6554
PRODUCT SPECIFICATION
4
REV. 1.1.3 3/8/02
Functional Description
This switching regulator is capable of sinking and sourcing
3A of current without an external heatsink. The ML6554
uses a power surface mount package (PSOP) that includes
an integrated heat slug. The heat can be piped through the
bottom of the device and onto the PCB (Figure 1).
The ML6554 integrates two power MOSFETs that can be
used to source and sink 3A of current while maintaining a
tight voltage regulation. Using the external feedback, the
output can be regulated well within 3% or less, depending on
the external components chosen. Separate voltage supply
inputs have been added to accommodate applications with
various power supplies for the databus and power buses, see
Figure 2.
Outputs
The output voltage pins (V
L1
, V
L2
) are tied to the databus,
address, or clock lines via an external inductor. See the
Applications section for recommendations. Output voltage
is determined by the V
CCQ
or VREF
IN
inputs.
Inputs
The input voltage pins (V
CCQ
or VREF
IN
) determine the
output voltages (V
L1
or V
L2
) . In the default mode, where
the VREF
IN
pin is floating, the output voltage is 50% of the
V
CCQ
input. V
CCQ
can be the reference voltage for the
databus.
Output voltage can also be selected by forcing a voltage at
the VREF
IN
pin. In this case, the output voltage follows the
voltage at the VREF
IN
input. Simple voltage dividers can be
used this case to produce a wide variety of output voltages
between 0.7V and V
DD
0.7V.
VREF Input and Output
The VREF
IN
input can be used to force a voltage at the
outputs (Inputs section, above). The VREF
OUT
pin is an
output pin that is driven by a small output buffer to provide
the V
REF
signal to other devices in the system. The output
buffer is capable of driving several output loads. The output
buffer can handle 3mA.
Other Supply Voltages
Several inputs are provide for the supply voltages: PV
DD1
,
PV
DD2
, AV
CC
, and V
DD
.
The PV
DD1
and PV
DD2
provide the power supply to the
power MOSFETs. V
DD
provides the voltage supply to the
digital sections, while AV
CC
supplies the voltage for the
analog sections. Again, see the Applications section for
recommendations.
Feedback Input
The V
FB
pin is an input that can be used for closed loop
compensation. This input is derived from the voltage output.
See application section for recommendation.
Figure 1. Cutaway view of PSOP Package
HEAT SLUG
PRODUCT SPECIFICATION
ML6554
REV. 1.1.3 3/8/02
5
Applications
Using the ML6554 for SSTL Bus Termination
The circuit schematic in Figure 2 shows a recommended
approach for constructing a bus terminating solution for an
SSTL-2 bus. This circuit can be used in PC memory and
Graphics memory applications as shown in Figures 4 and 5.
Note that the ML6554 can provide the voltage reference
(V
REF
) and terminating voltages (V
TT
). Using the layout
as shown in Figures 6, 7, and 8, and measuring the V
TT
performance using the test setup as described in Figure 9,
the ML6554 delivered a V
TT
20mV for 1A to 3A loads
(see Figure 10). Table 1 provides a recommended parts list
for the circuit in Figure 2.
Power Handling Capability of the PSOP
Package
Using the board layout shown in Figures 6, 7, and 8; solder-
ing the ML6554 to the board at zero LFPM the temperature
around the package measured 55C for 3A loads. Note that a
1 ounce copper plane was used in the board construction.
Airflow is not likely to be needed in the operation of this
device (assuming a board layout similar to that described
above). The power handling performance of the PSOP
package is shown by a study of the package manufacturer for
various airflow vs.
JA
conditions in Figure 11.
Bus Termination Solutions for Others Buses
Table 3 provides a summary of various bus termination V
REF
& V
TT
requirements. The ML6554 can be used for those
applications.
Figure 2.
16
15
14
13
12
11
10
9
U1
ML6554
VDD
PVDD1
VL1
PGND1
PGND2
VL2
PVDD2
DGND
AVCC
VCCQ
VREFOUT
AGND
SHDN
VREFIN
VFB
VDD
1
2
3
4
5
6
7
8
R3
100k
VCCQ
VREFOUT
TPI
VTT
2.5V TO 4V
SHDN
VREFIN
GND
GND
TO SDRAMS
C6
C7 1nF
C5
330
F
330
F
C4 0.1
F
R4 100k
R5 1k
C9 0.1
F
R2 100
R1 100
C8 0.1
F
C2
0.1
F
C1
820
F
F2V
OS-CON
L1 3.3
H C3 0.1F
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