1999 Fairchild Semiconductor Corporation
DS005905
www.fairchildsemi.com
October 1987
Revised July 1999
MM74C240
MM74C244
Inver
ti
ng
Non-
Inver
ti
ng
O
c
t
a
l
Buf
f
er
and
Lin
e
Dri
ver
wit
h
3-ST
A
T
E Outp
uts
MM74C240 MM74C244
Inverting Non-Inverting Octal Buffer and
Line Driver with 3-STATE Outputs
General Description
The MM74C240 and MM74C244 octal buffers and line
drivers are monolithic complementary MOS (CMOS) inte-
grated circuits with 3-STATE outputs. These outputs have
been specially designed to drive highly capacitive loads
such as bus-oriented systems. These devices have a fan
out of 6 low power Schottky loads. A high logic level on the
output disable control input G makes the outputs go into
the high impedance state.
Features
s
Wide supply voltage range (3V to 15V)
s
High noise immunity (0.45 V
CC
typ)
s
Low power consumption
s
High capacitive load drive capability
s
3-STATE outputs
s
Input protection
s
TTL compatibility
s
20-pin dual-in-line package
s
High speed 25 ns (typ.) @ 10V, 50 pF (MM74C244)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC
MM74C240
(Top View)
MM74C244
(Top View)
Order Number
Package Number
Package Description
MM74C240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
MM74C240N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74C244WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
MM74C244N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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2
MM
74
C
2
4
0
M
M
74C244
Logic Diagrams
MM74C240
MM74C244
Truth Tables
MM74C240
MM74C244
1
=
HIGH
0
=
LOW
X
=
Don't Care
Z
=
3-STATE
ODA
IA
OA
1
X
Z
1
X
Z
0
0
1
0
1
0
ODB
IB
OB
1
X
Z
1
X
Z
0
0
1
0
1
0
ODA
IA
OA
1
X
Z
1
X
Z
0
0
0
0
1
1
ODB
IB
OB
1
X
Z
1
X
Z
0
0
0
0
1
1
3
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MM74C240
MM74C244
Absolute Maximum Ratings
(Note 1)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Range"
they are not meant to imply that the devices should be operated at these
limits. The Electrical Characteristics table provides conditions for actual
device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range, unless otherwise noted
Voltage at Any Pin
-
0.3V to V
CC
+
0.3V
Operating Temperature Range
-
40
C to
+
85
C
Storage Temperature Range
-
65
C to
+
150
C
Power Dissipation
Dual-In-Line 700
mW
Small Outline
500 mW
Operating V
CC
Range
3V to 15V
Absolute Maximum V
CC
18V
Lead Temperature
(Soldering, 10 seconds)
260
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
IN(1)
Logical "1" Input Voltage
V
CC
=
5V
3.5
V
V
CC
=
10V
8.0
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
5V
1.5
V
V
CC
=
10V
2.0
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
5V, I
O
=
-
10
A
4.5
V
V
CC
=
10V, I
O
=
-
10
A
9.0
V
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
5V, I
O
=
10
A
0.5
V
V
CC
=
10V, I
O
=
10
A
1.0
V
I
OZ
3-STATE Output Current
V
CC
=
10V, OD
=
V
IH
10
A
I
IN(1)
Logical "1" Input Current
V
CC
=
15V, V
IN
=
15V
0.005
1.0
A
I
IN(0)
Logical "0" Input Current
V
CC
=
15V, V
IN
=
0V
-
1.0
-
0.005
A
I
CC
Supply Current
V
CC
=
15V
0.05
300
A
CMOS/LPTTL INTERFACE
V
IN(1)
Logical "1" Input Voltage
V
CC
=
4.75V
V
CC
-
1.5
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
4.75V
0.8
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
4.75V, I
O
=
-
450
A
V
CC
-
0.4
V
V
CC
=
4.75V, I
O
=
-
2.2 mA
2.4
V
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
4.75V, I
O
=
2.2 mA
0.4
V
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
Output Source Current
V
CC
=
5V, V
OUT
=
0V
-
14
-
30
mA
(P-Channel) T
A
=
25
C
V
CC
=
10V, V
OUT
=
0V
-
36
-
70
mA
T
A
=
25
C
I
SINK
Output Sink Current
V
CC
=
5V, V
OUT
=
V
CC
12
20
mA
(N-Channel) T
A
=
25
C
V
CC
=
10V, V
OUT
=
V
CC
48
70
mA
T
A
=
25
C
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4
MM
74
C
2
4
0
M
M
74C244
AC Electrical Characteristics
(Note 2)
T
A
=
25
C, C
L
=
50 pF, unless otherwise specified
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note,
AN-90.
Note 4: Capacitance is guaranteed by periodic testing.
Symbol Parameter
Conditions Min
Typ
Max
Units
t
PD(1)
,
t
PD(0)
Propagation Delay
(Data In to Out)
MM74C240 V
CC
=
5V, C
L
=
50 pF
60
90
ns
V
CC
=
10V, C
L
=
50 pF
40
70
ns
V
CC
=
5V, C
L
=
150 pF
80
110
ns
V
CC
=
10V, C
L
=
150 pF
60
90
ns
MM74C244 V
CC
=
5V, C
L
=
50 pF
45
70
ns
V
CC
=
10V, C
L
=
50 pF
25
50
ns
V
CC
=
5V, C
L
=
150 pF
60
90
ns
V
CC
=
10V, C
L
=
150 pF
40
70
ns
t
1H
, t
0H
Propagation Delay Output
R
L
=
1k, C
L
=
50 pF
Disable to High Impedance
V
CC
=
5V
45
80
ns
State (from a Logic Level)
V
CC
=
10V
35
60
ns
t
H1
, t
H0
Propagation Delay Output
R
L
=
1k, C
L
=
50 pF
Disable to Logic Level
V
CC
=
5V
50
90
ns
(from High Impedance State)
V
CC
=
10V
30
60
ns
t
T(HL)
, t
T(LH)
Transition Time
V
CC
=
5V, C
L
=
50 pF
45
80
ns
V
CC
=
10V, C
L
=
50 pF
30
60
ns
V
CC
=
5V, C
L
=
150 pF
75
140
ns
V
CC
=
10V, C
L
=
150 pF
50
100
ns
C
PD
Power Dissipation
(Note 3)
Capacitance
(Output Enabled per Buffer)
MM74C240
100
pF
MM74C244
100
pF
(Output Disabled per Buffer)
MM74C240
10
pF
MM74C244
0
pF
C
IN
Input Capacitance (Note 4)
V
IN
=
0V, f
=
1 MHz, T
A
=
25
C
10 pF
(Any Input)
C
O
Output Capacitance (Note 4)
V
IN
=
0V, f
=
1 MHz, T
A
=
25
C
10 pF
(Output Disabled)
5
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MM74C240
MM74C244
Typical Application
Typical Performance Characteristics
N-Channel Output Drive at 25
C
MM74C240
Propagation Delay vs. Load Capacitance
P-Channel Output Drive at 25
C
MM74C244
Propagation Delay vs. Load Capacitance
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6
MM
74
C
2
4
0
M
M
74C244
AC Test Circuits and Switching Time Waveforms
t
pd0,
t
pd1
t
1H
and t
H1
t
0H
and t
H0
Note: Delays measured with input t
r
, t
f
20 ns.
CMOS to CMOS
t
1H
and t
H1
Note: V
OH
is defined as the DC output high voltage when the device is
loaded with a 1 k
resistor to ground.
t
OH
and t
H0
Note: V
OL
is defined as the DC output low voltage when the device is loaded with a 1 k
resistor to V
CC
.
7
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MM74C240
MM74C244
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
Package Number M20B
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8
MM
74C24
0
M
M
74C244
I
nvert
i
ng
Non-
I
nvert
i
ng
Octal
Buf
f
e
r
a
nd Li
ne
D
r
ive
r
wi
th
3-
S
T
A
T
E
O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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