2005 Fairchild Semiconductor Corporation
DS005213
www.fairchildsemi.com
September 1983
Revised May 2005
MM74HC574
3-ST
A
T
E Oct
a
l
D-
T
ype Edg
e
-T
r
i
gger
ed F
l
i
p
-Fl
o
p
MM74HC574
3-STATE Octal D-Type Edge-Triggered Flip-Flop
General Description
The MM74HC574 high speed octal D-type flip-flops utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
These devices are positive edge triggered flip-flops. Data
at the D inputs, meeting the set-up and hold time require-
ments, are transferred to the Q outputs on positive going
transitions of the CLOCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 74HC logic family is speed, function, and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 18 ns
s
Wide operating voltage range: 2V6V
s
Low input current: 1
P
A maximum
s
Low quiescent current: 80
P
A maximum
s
Compatible with bus-oriented systems
s
Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
H
HIGH Level
L
LOW Level
X
Don't Care
n
Transition from LOW-to-HIGH
Z
High Impedance State
Q
0
The level of the output before steady state input conditions were
established
Order Number
Package Number
Package Description
MM74HC574WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC574MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC574N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Output
Clock
Data
Output
Control
L
n
H
H
L
n
L
L
L
L
X
Q
0
H
X
X
Z
www.fairchildsemi.com
2
MM
74HC574
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -- plastic "N" package:
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics
(Note 4)
Note 4: For a power supply of 5V
r
10% the worst-case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst-case V
IH
and V
IL
occur at V
CC
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst-case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Supply Voltage (V
CC
)
0.5 to
7.0V
DC Input Voltage (V
IN
)
1.5 to V
CC
1.5V
DC Output Voltage (V
OUT
)
0.5 to V
CC
0.5V
Clamp Diode Current (I
IK
, I
OK
)
r
20 mA
DC Output Current, per pin (I
OUT
)
r
35 mA
DC V
CC
or GND Current, per pin (I
CC
)
r
70 mA
Storage Temperature Range (T
STG
)
65
q
C to
150
q
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
q
C
Min
Max
Units
Supply Voltage (V
CC
)
2
6
V
DC Input or Output Voltage
0
V
CC
V
(V
IN
,V
OUT
)
Operating Temperature Range (T
A
)
40
85
q
C
Input Rise or Fall Times
(t
r
, t
f
)
V
CC
2.0V
1000
ns
V
CC
4.5V
500
ns
V
CC
6.0V
400
ns
Symbol
Parameter
Conditions
V
CC
T
A
25
q
C
T
A
40 to 85
q
C T
A
55 to 125
q
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level Input
2.0V
1.5
1.5
1.5
V
Voltage
4.5V
3.15
3.15
3.15
6.0V
4.2
4.2
4.2
V
IL
Maximum LOW Level Input
2.0V
0.5
0.5
0.5
V
Voltage 4.5V
1.35
1.35
1.35
6.0V
1.8
1.8
1.8
V
OH
Minimum HIGH Level Output
V
IN
V
IH
or V
IL
Voltage
|I
OUT
|
d
20
P
A
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
6.0V
6.0
5.9
5.9
5.9
V
IN
V
IH
or V
IL
|I
OUT
|
d
6.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT
|
d
7.8 mA
6.0V
5.7
5.48
5.34
5.2
V
OL
Maximum LOW Level Output
V
IN
V
IH
or V
IL
Voltage
|I
OUT
|
d
20
P
A
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
6.0V
0
0.1
0.1
0.1
V
IN
V
IH
or V
IL
|I
OUT
|
d
6.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|I
OUT
|
d
7.8 mA
6.0V
0.2
0.26
0.33
0.4
I
IN
Maximum Input Current
V
IN
V
CC
or GND
6.0V
r
0.1
r
1.0
r
1.0
P
A
I
OZ
Maximum 3-STATE
V
OUT
V
CC
or GND
Output Leakage Current
OC
V
IH
6.0V
r
0.5
r
5.0
r
10
P
A
I
CC
Maximum Quiescent Supply
V
IN
V
CC
or GND
Current
I
OUT
0
P
A
6.0V
8.0
80
160
P
A
'
I
CC
Quiescent Supply Current
V
CC
5.5V
OE
1.0
1.5
1.8
2.0
mA
per Input Pin
V
IN
2.4V
CLK
0.6
0.8
1.0
1.1
or 0.4V (Note 4)
DATA
0.4
0.5
0.6
0.7
3
www.fairchildsemi.com
MM74HC574
AC Electrical Characteristics
V
CC
5V, T
A
25
q
C, t
r
t
f
6 ns
AC Electrical Characteristics
V
CC
2.0
6.0V, C
L
50 pF, t
r
t
f
6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
f
MAX
Maximum Operating Frequency
60
33
MHz
t
PHL
, t
PLH
Maximum Propagation Delay, Clock to Q
C
L
45 pF
17
27
ns
t
PZH
, t
PZL
Maximum Output Enable Time
R
L
1 k
:
19
28
ns
C
L
45 pF
t
PHZ
, t
PLZ
Maximum Output Disable Time
R
L
1 k
:
14
25
ns
C
L
5 pF
t
S
Minimum Setup Time, Data to Clock
10
12
ns
t
H
Minimum Hold Time, Clock to Data
3
5
ns
t
W
Minimum Pulse Clock Width
8
15
ns
Symbol
Parameter
Conditions
V
CC
T
A
25
q
C
T
A
40 to 85
q
C T
A
55 to 125
q
C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating Frequency
C
L
50 pF
2.0V
33
28
23
MHz
4.5V
30
24
20
6.0V
35
28
23
t
PHL
, t
PLH
Maximum Propagation
C
L
50 pF
2.0V
18
30
38
45
ns
Delay, Clock to Q
C
L
150 pF
2.0V
51
155
194
233
C
L
50 pF
4.5V
13
23
29
35
ns
C
L
150 pF
4.5V
19
31
47
47
C
L
50 pF
6.0V
12
20
25
30
ns
C
L
150 pF
6.0V
18
27
34
41
t
PZH
, t
PZL
Maximum Output Enable
R
L
1 k
:
Time
C
L
50 pF
2.0V
22
30
38
45
ns
C
L
150 pF
2.0V
59
180
225
270
C
L
50 pF
4.5V
14
28
35
42
ns
C
L
150 pF
4.5V
20
36
45
54
C
L
50 pF
6.0V
12
24
30
36
ns
C
L
150 pF
6.0V
18
31
39
47
t
PHZ
, t
PLZ
Maximum Output Disable Time
R
L
1 k
:
2.0V
15
30
38
45
ns
C
L
50 pF
4.5V
12
25
31
38
6.0V
10
21
27
32
t
S
Minimum Setup Time
2.0V
6
12
15
18
ns
Data to Clock
4.5V
20
25
30
6.0V
17
21
25
t
H
Minimum Hold Time
2.0V
1
5
6
8
ns
Clock to Data
4.5V
0
0
0
6.0V
0
0
0
t
THL
, t
TLH
Maximum Output Rise
C
L
50 pF
2.0V
6
12
15
18
ns
and Fall Time
4.5V
7
12
15
18
6.0V
6
10
13
15
t
W
Minimum Clock Pulse Width
2.0V
30
15
20
24
ns
4.5V
9
16
20
24
6.0V
8
14
18
20
t
r
,t
f
Maximum Clock Input Rise
2.0V
1000
1000
1000
ns
and Fall Time
4.5V
500
500
500
6.0V
400
400
400
C
PD
Power Dissipation Capacitance
OC
V
CC
5
pF
(Note 5) (per latch)
OC
GND
58
C
IN
Maximum Input Capacitance
5
10
10
10
pF
www.fairchildsemi.com
4
MM
74HC574
AC Electrical Characteristics
(Continued)
Note 5: C
PD
determines the no load dynamic power consumption, P
D
C
PD
V
CC
2
f
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
C
PD
V
CC
f
I
CC
.
Symbol
Parameter
Conditions
V
CC
T
A
25
q
C
T
A
40 to 85
q
C T
A
55 to 125
q
C
Units
Typ
Guaranteed Limits
C
OUT
Maximum Output
15
20
20
20
pF
Capacitance
5
www.fairchildsemi.com
MM74HC574
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
PDF 
ZIP