www.docs.chipfind.ru
October 1987
Revised January 1999
MM74C74 Dual D-T
ype Fli
p
-Fl
o
p
1999 Fairchild Semiconductor Corporation
DS005885.prf
www.fairchildsemi.com
MM74C74
Dual D-Type Flip-Flop
General Description
The MM74C74 dual D-type flip-flop is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement transistors. Each flip-flop
has independent data, preset, clear and clock inputs and Q
and Q outputs. The logic level present at the data input is
transferred to the output during the positive going transition
of the clock pulse. Preset or clear is independent of the
clock and accomplished by a low level at the preset or clear
input.
Features
s
Supply voltage range:
3V to 15V
s
Tenth power TTL compatible:
Drive 2 LPT
2
L loads
s
High noise immunity:
0.45 V
CC
(typ.)
s
Low power:
50 nW (typ.)
s
Medium speed operation:
10 MHz (typ.) with 10V
supply
Applications
Automotive
Data terminals
Instrumentation
Medical electronics
Alarm system
Industrial electronics
Remote metering
Computers
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Note: A logic "0" on clear sets Q to logic "0".
A logic "0" on preset sets Q to logic "1".
Top View
Truth Table
Note 1: No change in output from previous state.
Order Number
Package Number
Package Description
MM74C74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
MM74C74N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Preset
Clear
Q
n
Q
n
0
0
0
0
0
1
1
0
1
0
0
1
1
1
Q
n
(Note 1)
Q
n
(Note 1)
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2
MM
74C74
Logic Diagram
3
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MM74C74
Absolute Maximum Ratings
(Note 2)
Note 2: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Tempera-
ture Range" they are not meant to imply that the devices should be oper-
ated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Voltage at Any Pin (Note 2)
-
0.3V to V
CC
+
0.3V
Operating Temperature Range
-
40
C to
+
85
C
Storage Temperature Range
-
65
C to
+
150
C
Power Dissipation
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature
(Soldering, 10 seconds)
260
C
Operating V
CC
Range
3V to 15V
V
CC
(Max)
18V
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
IN(1)
Logical "1" Input Voltage
V
CC
=
5V
3.5
V
V
CC
=
10V
80
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
5V
1.5
V
V
CC
=
10V
2.0
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
5V
4.5
V
V
CC
=
10V
9.0
V
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
5V
0.5
V
V
CC
=
10V
1.0
V
I
IN(1)
Logical "1" Input Current
V
CC
=
15V
1.0
A
I
IN(0)
Logical "0" Input Current
V
CC
=
15V
-
1.0
A
I
CC
Supply Current
V
CC
=
15V
0.05
60
A
CMOS/LPTTL INTERFACE
V
IN(1)
Logical "1" Input Voltage
V
CC
=
4.75V
V
CC
-
1.5
V
IN(0)
Logical "0" Input Voltage
V
CC
=
4.75V
0.8
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
4.75V, I
D
=
-
360
A
2.4
V
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
4.75V, I
D
=
360
A
0.4
V
OUTPUT DRIVE (See Family Characteristics Data Sheet)
I
SOURCE
Output Source Current
V
CC
=
5V, V
IN(0)
=
0V
-
1.75
mA
T
A
=
25
C, V
OUT
=
0V
I
SOURCE
Output Source Current
V
CC
=
10V, V
IN(0)
=
0V
-
8.0
mA
T
A
=
25
C, V
OUT
=
0V
I
SINK
Output Sink Current
V
CC
=
5V, V
IN(1)
=
5V
1.75
mA
T
A
=
25
C, V
OUT
=
V
CC
I
SINK
Output Sink Current
V
CC
=
10V, V
IN(1)
=
10V
8.0
mA
T
A
=
25
C, V
OUT
=
V
CC
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4
MM
74C74
AC Electrical Characteristics
(Note 3)
T
A
=
25
C, C
L
=
50 pF, unless otherwise noted
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note--
AN-90.
Typical Applications
Ripple Counter (Divide by 2
n
)
Shift Register
74C Compatibility
Guaranteed Noise Margin as a Function of V
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
C
IN
Input Capacitance
Any Input (Note 4)
5.0
pF
t
pd
Propagation Delay Time to a
V
CC
=
5V
180
300
ns
Logical "0" t
pd0
or Logical "1"
V
CC
=
10V
70
110
ns
t
pd1
from Clock to Q or Q
t
pd
Propagation Delay Time to a
V
CC
=
5V
180
300
ns
Logical "0" from Preset or Clear
V
CC
=
10V
70
110
ns
t
pd
Propagation Delay Time to a
V
CC
=
5V
250
400
ns
Logical "1" from Preset or Clear
V
CC
=
10V
100
150
ns
t
S0
, t
S1
Time Prior to Clock Pulse that
V
CC
=
5V
100
50
ns
Data Must be Present t
SETUP
V
CC
=
10V
40
20
ns
t
H0
, t
H1
Time after Clock Pulse that
V
CC
=
5V
-
20
0
ns
Data Must be Held
V
CC
=
10V
-
8.0
0
ns
t
PW1
Minimum Clock Pulse
V
CC
=
5V
100
250
ns
Width (t
WL
=
t
WH
)
V
CC
=
10V
40
100
ns
t
PW2
Minimum Preset and
V
CC
=
5V
100
160
ns
Clear Pulse Width
V
CC
=
10V
40
70
ns
t
r
, t
f
Maximum Clock Rise
V
CC
=
5V
15.0
s
and Fall Time
V
CC
=
10V
5.0
s
f
MAX
Maximum Clock Frequency
V
CC
=
5V
2.0
3.5
MHz
V
CC
=
10V
5.0
8.0
MHz
C
PD
Power Dissipation Capacitance
(Note 5)
40
pF
5
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MM74C74
Switching Time Waveform
CMOS to CMOS
t
r
=
t
f
=
20 ns
AC Test Circuit
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