September 1983
Revised February 1999
MM74HC125/
M
M
74HC126 3-
ST
A
T
E Q
uad
Buf
f
er
s
1999 Fairchild Semiconductor Corporation
DS005308.prf
www.fairchildsemi.com
MM74HC125/MM74HC126
3-STATE Quad Buffers
General Description
The MM74HC125 and MM74HC126 are general purpose
3-STATE high speed non-inverting buffers utilizing
advanced silicon-gate CMOS technology. They have high
drive current outputs which enable high speed operation
even when driving large bus capacitances. These circuits
possess the low power dissipation of CMOS circuitry, yet
have speeds comparable to low power Schottky TTL cir-
cuits. Both circuits are capable of driving up to 15 low
power Schottky inputs.
The MM74HC125 require the 3-STATE control input C to
be taken high to put the output into the high impedance
condition, whereas the MM74HC126 require the control
input to be low to put the output into high impedance.
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and ground.
Features
s
Typical propagation delay: 13 ns
s
Wide operating voltage range: 26V
s
Low input current: 1
A maximum
s
Low quiescent current: 80
A maximum (74HC)
s
Fanout of 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. (Tape and Reel not available in N14A.)
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View (MM74HC125)
Top View (MM74HC126)
Truth Tables
Order Number
Package Number
Package Description
MM74HC125M M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body
MM74HC125SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC125MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC125N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HC126M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body
MM74HC126SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC126MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC126N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Inputs
Output
A
C
Y
H
L
H
L
L
L
X
H
Z
Inputs
Output
A
C
Y
H
H
H
L
H
L
X
L
Z
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2
M
M
74HC125/
MM
74HC126
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -- plastic "N" package:
-
12 mW/
C from 65
C to 85
C.
DC Electrical Characteristics
(Note 4)
Note 4: For a power supply of 5V
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current
(I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
20 mA
DC Output Current, per pin (I
OUT
)
35 mA
DC V
CC
or GND Current, per pin
(I
CC
)
70 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
C
Min Max Units
Supply Voltage (V
CC
)
2
6
V
DC Input or Output Voltage
0
V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
-
40
+
85
C
Input Rise or Fall Times (t
r
, t
f
)
V
CC
=
2.0V
1000
ns
V
CC
=
4.5V
500
ns
V
CC
=
6.0V
400
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
40 to 125
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
V
IL
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
2.0V
2.0
1.9
1.9
1.9
V
Output Voltage
|I
OUT
|
20
A
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
V
IN
=
V
IH
or V
IL
|I
OUT
|
6.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT
|
7.8 mA
6.0V
5.7
5.48
5.34
5.2
V
V
OL
Maximum LOW Level
V
IN
=
V
IH
or V
IL
2.0V
0
0.1
0.1
0.1
V
Output Voltage
|I
OUT
|
20
A
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
V
IN
=
V
IH
or V
IL
|I
OUT
|
6.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|I
OUT
|
7.8 mA
6.0V
0.2
0.26
0.33
0.4
V
I
OZ
Maximum 3-STATE Output
V
IN
=
V
IH
or V
IL
6.0V
0.5
5
10
A
Leakage Current
V
OUT
=
V
CC
or GND
C
n
=
Disabled
I
IN
Maximum Input Current
V
IN
=
V
CC
or GND
6.0V
0.1
1.0
1.0
A
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
6.0V
8.0
80
160
A
Supply Current
I
OUT
=
0
A
3
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MM74HC125/
M
M
74HC126
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
C, C
L
=
45 pF, t
r
=
t
f
=
6 ns
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Note 5: C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
t
PHL
, t
PLH
Maximum
13
18
ns
Propagation Delay Time
t
PZH
Maximum R
L
=
1 k
13
25
ns
Output Enable Time to HIGH Level
t
PHZ
Maximum R
L
=
1 k
17
25
ns
Output Disable Time from HIGH Level
C
L
=
5 pF
t
PZL
Maximum R
L
=
1 k
18
25
ns
Output Enable Time to LOW Level
t
PLZ
Maximum R
L
=
1 k
13
25
ns
Output Disable Time from LOW Level
C
L
=
5 pF
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
40 to 125
C
Units
Typ
Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation
2.0V
40
100
125
150
ns
Delay Time
4.5V
14
20
25
30
ns
6.0V
12
17
21
25
ns
t
PLH
, t
PHL
Maximum Propagation
C
L
=
150 pF
2.0V
35
130
163
195
ns
Delay Time
4.5V
14
26
33
39
ns
6.0V
12
22
28
39
ns
t
PZH
, t
PZL
Maximum Output
R
L
=
1 k
2.0V
25
125
156
188
ns
Enable Time
4.5V
14
25
31
38
ns
6.0V
12
21
26
31
ns
t
PHZ
, t
PLZ
Maximum Output
R
L
=
1 k
2.0V
25
125
156
188
ns
Disable Time
4.5V
14
25
31
38
ns
6.0V
12
21
26
31
ns
t
PZL
, t
PZH
Maximum Output
C
L
=
150 pF
2.0V
35
140
175
210
ns
Enable Time
R
L
=
1 k
4.5V
15
28
35
42
ns
6.0V
13
24
30
36
ns
t
TLH
, t
THL
Maximum Output
C
L
=
50 pF
2.0V
30
60
75
90
ns
Rise and Fall Time
4.5V
7
12
15
18
ns
6.0V
6
10
13
15
ns
C
IN
Input Capacitance
5
10
10
10
pF
C
OUT
Output Capacitance Outputs
15
20
20
20
pF
C
PD
Power Dissipation
(per gate)
Capacitance (Note 5)
Enabled
45
pF
Disabled
6
pF
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4
M
M
74HC125/
MM
74HC126
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
www.fairchildsemi.com
MM74HC125/
M
M
74HC126
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC125/
M
M
74HC126 3-
S
T
A
T
E
Quad Buff
ers
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
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